DSP56321RMSLASHD datasheet(76/88 Pages) NXP

76 / 88 page

A-6

Power Consumption Benchmark

;

M_TX10 EQU $FFFFAC

; SSI1 Transmit Data Register 0

M_TX11 EQU $FFFFAB

; SSI1 Transmit Data Register 1

M_TX12 EQU $FFFFAA

; SSI1 Transmit Data Register 2

M_TSR1 EQU $FFFFA9

; SSI1 Time Slot Register

M_RX1 EQU $FFFFA8

; SSI1 Receive Data Register

M_SSISR1 EQU $FFFFA7

; SSI1 Status Register

M_CRB1 EQU $FFFFA6

; SSI1 Control Register B

M_CRA1 EQU $FFFFA5

; SSI1 Control Register A

M_TSMA1 EQU $FFFFA4

; SSI1 Transmit Slot Mask Register A

M_TSMB1 EQU $FFFFA3

; SSI1 Transmit Slot Mask Register B

M_RSMA1 EQU $FFFFA2

; SSI1 Receive Slot Mask Register A

M_RSMB1 EQU $FFFFA1

; SSI1 Receive Slot Mask Register B

;

SSI Control Register A Bit Flags

M_PM EQU $FF

; Prescale Modulus Select Mask (PM0-PM7)

M_PSR EQU 11

; Prescaler Range

M_DC EQU $1F000

; Frame Rate Divider Control Mask (DC0-DC7)

M_ALC EQU 18

; Alignment Control (ALC)

M_WL EQU $380000

; Word Length Control Mask (WL0-WL7)

M_SSC1 EQU 22

; Select SC1 as TR #0 drive enable (SSC1)

;

SSI Control Register B Bit Flags

M_OF EQU $3

; Serial Output Flag Mask

M_OF0 EQU 0

; Serial Output Flag 0

M_OF1 EQU 1

; Serial Output Flag 1

M_SCD EQU $1C

; Serial Control Direction Mask

M_SCD0 EQU 2

; Serial Control 0 Direction

M_SCD1 EQU 3

; Serial Control 1 Direction

M_SCD2 EQU 4

; Serial Control 2 Direction

M_SCKD EQU 5

; Clock Source Direction

M_SHFD EQU 6

; Shift Direction

M_FSL EQU $180

; Frame Sync Length Mask (FSL0-FSL1)

M_FSL0 EQU 7

; Frame Sync Length 0

M_FSL1 EQU 8

; Frame Sync Length 1

M_FSR EQU 9

; Frame Sync Relative Timing

M_FSP EQU 10

; Frame Sync Polarity

M_CKP EQU 11

; Clock Polarity

M_SYN EQU 12

; Sync/Async Control

M_MOD EQU 13

; SSI Mode Select

M_SSTE EQU $1C000

; SSI Transmit enable Mask

M_SSTE2 EQU 14

; SSI Transmit #2 Enable

M_SSTE1 EQU 15

; SSI Transmit #1 Enable

M_SSTE0 EQU 16

; SSI Transmit #0 Enable

M_SSRE EQU 17

; SSI Receive Enable

M_SSTIE EQU 18

; SSI Transmit Interrupt Enable

M_SSRIE EQU 19

; SSI Receive Interrupt Enable

M_STLIE EQU 20

; SSI Transmit Last Slot Interrupt Enable

M_SRLIE EQU 21

; SSI Receive Last Slot Interrupt Enable

M_STEIE EQU 22

; SSI Transmit Error Interrupt Enable

M_SREIE EQU 23

; SI Receive Error Interrupt Enable

;

SSI Status Register Bit Flags

M_IF EQU $3

; Serial Input Flag Mask

M_IF0 EQU 0

; Serial Input Flag 0

M_IF1 EQU 1

; Serial Input Flag 1

M_TFS EQU 2

; Transmit Frame Sync Flag

M_RFS EQU 3

; Receive Frame Sync Flag

M_TUE EQU 4

; Transmitter Underrun Error FLag

M_ROE EQU 5

; Receiver Overrun Error Flag

M_TDE EQU 6

; Transmit Data Register Empty

M_RDF EQU 7

; Receive Data Register Full

;

SSI Transmit Slot Mask Register A

M_SSTSA EQU $FFFF

; SSI Transmit Slot Bits Mask A (TS0-TS15)

;

SSI Transmit Slot Mask Register B

M_SSTSB EQU $FFFF

; SSI Transmit Slot Bits Mask B (TS16-TS31)

;

SSI Receive Slot Mask Register A

M_SSRSA EQU $FFFF

; SSI Receive Slot Bits Mask A (RS0-RS15)

;

SSI Receive Slot Mask Register B

M_SSRSB EQU $FFFF

; SSI Receive Slot Bits Mask B (RS16-RS31)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56321RM/D 数据表(PDF) 76 Page - NXP Semiconductors

DSP56321RM/D 数据表(HTML) 76 Page - NXP Semiconductors

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