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DSP56321RM/D 数据表(PDF) 40 Page - NXP Semiconductors |
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DSP56321RM/D 数据表(HTML) 40 Page - NXP Semiconductors |
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40 / 88 page  2-16 AC Electrical Characteristics 2.5.6 Host Interface Timing Table 2-10. Host Interface Timings1,2,12 No. Characteristic10 Expression 220 MHz 240 MHz Unit Min Max Min Max 317 Read data strobe assertion width5 HACK assertion width TC + T318 9.05 —8.30— ns 318 Read data strobe deassertion width5 HACK deassertion width T318 4.5 — 4.13 — ns 319 Read data strobe deassertion width5 after “Last Data Register” reads8,11, or between two consecutive CVR, ICR, or ISR reads3 HACK deassertion width after “Last Data Register” reads8,11 2.5 × T C + 3.3 14.7 — 13.7 — ns 320 Write data strobe assertion width6 6.0 — 5.5 — ns 321 Write data strobe deassertion width8 HACK write deassertion width • after ICR, CVR and “Last Data Register” writes • after IVR writes, or after TXH:TXM:TXL writes (with HLEND= 0), or after TXL:TXM:TXH writes (with HLEND = 1) 2.5 × T C + 3.3 14.7 7.5 — — 13.7 6.88 — — ns ns 322 HAS assertion width 4.5 — 4.13 — ns 323 HAS deassertion to data strobe assertion4 0.0 — 0.0 — ns 324 Host data input setup time before write data strobe deassertion6 4.5 — 4.13 — ns 325 Host data input hold time after write data strobe deassertion6 1.5 — 1.38 — ns 326 Read data strobe assertion to output data active from high impedance5 HACK assertion to output data active from high impedance 1.5 — 1.38 — ns 327 Read data strobe assertion to output data valid5 HACK assertion to output data valid — 13.45 — 12.32 ns 328 Read data strobe deassertion to output data high impedance5 HACK deassertion to output data high impedance —4.5 — 4.13 ns 329 Output data hold time after read data strobe deassertion5 Output data hold time after HACK deassertion 1.5 — 1.38 — ns 330 HCS assertion to read data strobe deassertion5 TC + T318 9.05 — 8.30 — ns 331 HCS assertion to write data strobe deassertion6 4.5 — 4.13 — ns 332 HCS assertion to output data valid — 11.04 — 10.12 ns 333 HCS hold time after data strobe deassertion4 0.0 — 0.0 — ns 334 Address (HAD[0–7]) setup time before HAS deassertion (HMUX=1) 2.1 — 1.93 — ns 335 Address (HAD[0–7]) hold time after HAS deassertion (HMUX=1) 1.5 — 1.38 — ns 336 HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W setup time before data strobe assertion4 • Read •Write 0 2.1 — — 0 1.93 — — ns ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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