DSP56321RMSLASHD datasheet(79/88 Pages) NXP

79 / 88 page

A-9

Power Consumption Benchmark

M_DDR2 EQU $FFFFE6 ; DMA2 Destination Address Register

M_DCO2 EQU $FFFFE5 ; DMA2 Counter

M_DCR2 EQU $FFFFE4 ; DMA2 Control Register

;

M_DSR3 EQU $FFFFE3 ; DMA3 Source Address Register

M_DDR3 EQU $FFFFE2 ; DMA3 Destination Address Register

M_DCO3 EQU $FFFFE1 ; DMA3 Counter

M_DCR3 EQU $FFFFE0 ; DMA3 Control Register

;

M_DSR4 EQU $FFFFDF ; DMA4 Source Address Register

M_DDR4 EQU $FFFFDE ; DMA4 Destination Address Register

M_DCO4 EQU $FFFFDD ; DMA4 Counter

M_DCR4 EQU $FFFFDC ; DMA4 Control Register

;

M_DSR5 EQU $FFFFDB ; DMA5 Source Address Register

M_DDR5 EQU $FFFFDA ; DMA5 Destination Address Register

M_DCO5 EQU $FFFFD9 ; DMA5 Counter

M_DCR5 EQU $FFFFD8 ; DMA5 Control Register

;

DMA Control Register

M_DSS EQU $3

; DMA Source Space Mask (DSS0-Dss1)

M_DSS0 EQU 0

; DMA Source Memory space 0

M_DSS1 EQU 1

; DMA Source Memory space 1

M_DDS EQU $C

; DMA Destination Space Mask (DDS-DDS1)

M_DDS0 EQU 2

; DMA Destination Memory Space 0

M_DDS1 EQU 3

; DMA Destination Memory Space 1

M_DAM EQU $3f0 ; DMA Address Mode Mask (DAM5-DAM0)

M_DAM0

EQU 4

; DMA Address Mode 0

M_DAM1

EQU 5

; DMA Address Mode 1

M_DAM2

EQU 6

; DMA Address Mode 2

M_DAM3

EQU 7

; DMA Address Mode 3

M_DAM4

EQU 8

; DMA Address Mode 4

M_DAM5

EQU 9

; DMA Address Mode 5

M_D3D EQU 10

; DMA Three Dimensional Mode

M_DRS EQU $F800; DMA Request Source Mask (DRS0-DRS4)

M_DCON EQU 16

; DMA Continuous Mode

M_DPR EQU $60000; DMA Channel Priority

M_DPR0 EQU 17

; DMA Channel Priority Level (low)

M_DPR1 EQU 18

; DMA Channel Priority Level (high)

M_DTM EQU $380000; DMA Transfer Mode Mask (DTM2-DTM0)

M_DTM0 EQU 19

; DMA Transfer Mode 0

M_DTM1 EQU 20

; DMA Transfer Mode 1

M_DTM2 EQU 21

; DMA Transfer Mode 2

M_DIE EQU 22

; DMA Interrupt Enable bit

M_DE EQU 23

; DMA Channel Enable bit

;

DMA Status Register

M_DTD EQU $3F

; Channel Transfer Done Status MASK (DTD0-DTD5)

M_DTD0 EQU 0

; DMA Channel Transfer Done Status 0

M_DTD1 EQU 1

; DMA Channel Transfer Done Status 1

M_DTD2 EQU 2

; DMA Channel Transfer Done Status 2

M_DTD3 EQU 3

; DMA Channel Transfer Done Status 3

M_DTD4 EQU 4

; DMA Channel Transfer Done Status 4

M_DTD5 EQU 5

; DMA Channel Transfer Done Status 5

M_DACT EQU

; DMA Active State

M_DCH EQU

$E00; DMA Active Channel Mask (DCH0-DCH2)

M_DCH0 EQU

; DMA Active Channel 0

M_DCH1 EQU

10 ; DMA Active Channel 1

M_DCH2 EQU

11 ; DMA Active Channel 2

;------------------------------------------------------------------------

;

EQUATES for Enhanced Filter Co-Processor (EFCOP)

;

;------------------------------------------------------------------------

M_FDIR

EQU

$FFFFB0

; EFCOP Data Input Register

M_FDOR

EQU

$FFFFB1

; EFCOP Data Output Register

M_FKIR

EQU

$FFFFB2

; EFCOP K-Constant Register

M_FCNT

EQU

$FFFFB3

; EFCOP Filter Counter

M_FCSR

EQU

$FFFFB4

; EFCOP Control Status Register

M_FACR

EQU

$FFFFB5

; EFCOP ALU Control Register

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56321RM/D 数据表(PDF) 79 Page - NXP Semiconductors

DSP56321RM/D 数据表(HTML) 79 Page - NXP Semiconductors

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