DSP56321RMSLASHD datasheet(41/88 Pages) NXP

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2-17

AC Electrical Characteristics

337

HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W hold time

after data strobe deassertion4

1.5

—

1.38

—

338

Delay from read data strobe deassertion to host request

assertion for “Last Data Register” read5, 7, 8

TC + 2.64

7.19

—

6.81

—

339

Delay from write data strobe deassertion to host request

assertion for “Last Data Register” write6, 7, 8

1.5

× T

C + 2.64

9.47

—

8.9

—

340

Delay from data strobe assertion to host request deassertion

for “Last Data Register” read or write (HROD=0)4, 7, 8

—

11.04

—

10.12

341

Delay from data strobe assertion to host request deassertion

for “Last Data Register” read or write (HROD=1, open drain

host request)4, 7, 8, 9

—

300.0

—

300.0

Notes:

See the Programmer’s Model section in the chapter on the HI08 in the

DSP56321 User’s Manual.

In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.

This timing is applicable only if two consecutive reads from one of these registers are executed.

The data strobe is Host Read (HRD) or Host Write (HWR) in the Dual Data Strobe mode and Host Data Strobe

(HDS) in the Single Data Strobe mode.

The read data strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

The write data strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

The host request is HREQ in the Single Host Request mode and HRRQ and HTRQ in the Double Host Request

mode.

The “Last Data Register” is the register at address $7, which is the last location to be read or written in data

transfers. This is RXL/TXL in the Big Endian mode (HLEND = 0; HLEND is the Interface Control Register bit

7—ICR[7]), or RXH/TXH in the Little Endian mode (HLEND = 1).

In this calculation, the host request signal is pulled up by a 4.7 k

Ω resistor in the Open-drain mode.

10. VCCQH = 3.3 V ± 0.3 V, VCCQL = 1.6 V ± 0.1 V; TJ = 0°C to +85°C, CL = 50 pF

11.

This timing is applicable only if a read from the “Last Data Register” is followed by a read from the RXL, RXM, or

RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ signal.

12. After the external host writes a new value to the ICR, the HI08 will be ready for operation after three DSP clock

cycles (3

× Tc).

Figure 2-13. Host Interrupt Vector Register (IVR) Read Timing Diagram

Table 2-10. Host Interface Timings1,2,12 (Continued)

No.

Characteristic10

Expression

220 MHz

240 MHz

Unit

Min

Max

Min

Max

HACK

H[0–7]

HREQ

329

317

318

328

326

327

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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