ADE7169ASTF16 datasheet(41/140 Pages) AD

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Preliminary Technical Data

ADE7169F16

Rev. PrD | Page 41 of 140

CYCEND

Logic one indicates the end of the energy accumulation over an integer number of half

line cycles.

ZXTO

Logic one indicates that no zero crossing on the line voltage happened for the last

ZXTOUT half line cycles.

Logic one indicates detection of a zero crossing in the voltage channel.

Table 38. Interrupt Enable Register 1 SFR (MIRQENL, 0xD9)

Bit

Location

Interrupt Flag

Description

7-6

Reserved

Reserved.

FAULTSIGN

When this bit is set, the FAULTSIGN bit set creates a pending ADE interrupt to the 8052

core.

VARSIGN

When this bit is set, the VARSIGN bit set creates a pending ADE interrupt to the 8052 core.

APSIGN

When this bit is set, the APSIGN bit set creates a pending ADE interrupt to the 8052 core.

VANOLOAD

When this bit is set, the VANOLOAD bit set creates a pending ADE interrupt to the 8052

core.

RNOLOAD

When this bit is set, the RNOLOAD bit set creates a pending ADE interrupt to the 8052

core.

APNOLOAD

When this bit is set, the APNOLOAD bit set creates a pending ADE interrupt to the 8052

core.

Table 39. Interrupt Enable Register 2 SFR (MIRQENM, 0xDA)

Bit

Location

Interrupt Flag

Description

CF2

When this bit is set, a CF2 pulse issued creates a pending ADE interrupt to the 8052 core.

CF1

When this bit is set, a CF1 pulse issued creates a pending ADE interrupt to the 8052 core.

VAEOF

When this bit is set, the VAEOF flag set creates a pending ADE interrupt to the 8052 core.

REOF

When this bit is set, the REOF flag set creates a pending ADE interrupt to the 8052 core.

AEOF

When this bit is set, the AEOF flag set creates a pending ADE interrupt to the 8052 core.

VAEHF

When this bit is set, the VAEHF flag set creates a pending ADE interrupt to the 8052 core.

REHF

When this bit is set, the REHF flag set creates a pending ADE interrupt to the 8052 core.

AEHF

When this bit is set, the AEHF flag set creates a pending ADE interrupt to the 8052 core.

Table 40. Interrupt Enable Register 3 SFR (MIRQENH, 0xDB)

Bit

Location

Interrupt Flag

Description

7-6

Reserved

WFSM

When this bit is set, the WFSM flag set creates a pending ADE interrupt to the 8052 core.

PKI

When this bit is set, the PKI flag set creates a pending ADE interrupt to the 8052 core.

PKV

When this bit is set, the PKV flag set creates a pending ADE interrupt to the 8052 core..

CYCEND

When this bit is set, the CYCEND flag set creates a pending ADE interrupt to the 8052 core.

ZXTO

When this bit is set, the ZXTO flag set creates a pending ADE interrupt to the 8052 core.

When this bit is set, the ZX flag set creates a pending ADE interrupt to the 8052 core.

ANALOG INPUTS

The ADE7169F16 has two fully differential voltage input

channels. The maximum differential input voltage for input

pairs VP/VN and IP/IN are ±0.5 V. In addition, the maximum

signal level on analog inputs for VP/VN and IP/ IN is ±0.5 V

with respect to AGND.

Each analog input channel has a PGA (programmable gain

amplifier) with possible gain selections of 1, 2, 4, 8, and 16. The

gain selections are made by writing to the GAIN register in the

Energy Measurement Register List—see Table 33 and Figure 17.

Bits 0 to 2 select the gain for the PGA in the current channel, and

the gain selection for the PGA in voltage channel is made via

Bits 5 to 7. Figure 16 shows how a gain selection for the current

channel is made using the gain register.

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