ADE7169ASTF16 datasheet(63/140 Pages) AD

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Preliminary Technical Data

ADE7169F16

Rev. PrD | Page 63 of 140

VADIV[7:0]

LPF1

LVAHR [23:0]

LVAHR REGISTER IS

UPDATED EVERY LINCYC

ZERO CROSSINGS WITH THE

TOTAL APPARENT ENERGY

DURING THAT DURATION

APPARENT

POWER

FROM

VOLTAGE CHANNEL

ADC

LINCYC [15:0]

ZERO-CROSSING

DETECTION

CALIBRATION

CONTROL

Figure 51. ADE7169F16 Line cycle Apparent Energy Accumulation

Apparent power no-Load detection

The ADE7169F16 includes a no-load threshold feature on the

apparent energy that eliminates any creep effects in the meter.

The ADE7169F16 accomplishes this by not accumulating

energy if the multiplier output is below the no-load threshold.

When the apparent power is below the no-load threshold, the

VANOLOAD flag in the Interrupt Status Register 1 SFR

(MIRQSTL, 0xDC) is set. If the VANOLOAD bit is set in the

Interrupt Enable Register 1 SFR (MIRQENL, 0xD9), the 8052

core has a pending ADE interrupt. The ADE interrupt stays

active until the APNOLOAD status bit is cleared—see Energy

measurement interrupts section.

The No-load threshold level is selectable by setting bits

VANOLOAD in the NLMODE register (0x0E). Setting these

bits to 0b00 disable the no-load detection and setting them to

0b01, 0b10 or 0b11 set the no-load detection threshold to

0.030%, 0.015% and 0.0075% of the full-scale output frequency

of the multiplier respectively.

This no-load threshold can also be applied to the Irms pulse

output when selected. The level of no-load threshold is the same

as for the Apparent energy in this case.

ENERGY-TO-FREQUENCY CONVERSION

ADE7169F16 also provides two energy-to-frequency

conversions for calibration purposes. After initial calibration at

manufacturing, the manufacturer or end customer often verify

the energy meter calibration. One convenient way to verify the

meter calibration is for the manufacturer to provide an output

frequency, which is proportional to the active, reactive,

apparent power or Irms under steady load conditions. This

output frequency can provide a simple, single-wire, optically

isolated interface to external calibration equipment. Figure 52

illustrates the energy-to-frequency conversion in the

ADE7169F16.

CFx

Pulse

output

CFxNUM

CFxDEN

DFC

VAR

Irms

CFxSEL[1:0]

WATT

VARMSCFCON

MODE2 Register 0x0C

Figure 52. ADE7169F16 Energy-to-Frequency Conversion

Two digital-to-frequency converters (DFC) are used to generate

the pulsed outputs. When WDIV =0 or 1, the DFC generates a

pulse each time 1 LSB in the energy register is accumulated. An

output pulse is generated when CFxDEN/CFxNUM number of

pulses are generated at the DFC output. Under steady load

conditions, the output frequency is proportional to the active,

reactive, Apparent power or Irms depending on the CFxSEL bit

in the MODE2 register (0x0C).

Both pulse outputs can be enabled or disabled by clearing or

setting respectively bits DISCF1 and DISCF2 in the MODE1

Both pulse outputs set a separate flag in the Interrupt Status

CF2 enable bits in the Interrupt Enable Register 2 SFR

(MIRQENM, 0xDA) are set, the 8052 core has a pending ADE

interrupt. The ADE interrupt stays active until the CF1 or CF2

status bits are cleared—see Energy measurement interrupts

section.

Pulse output configuration

The two pulse outputs circuitry have separate configuration bits

in the MODE2 register (0x0C). Setting CFxSEL bits to 0b00,

0b01 or 0b1x configure the DFC to create a pulse output

ADE7169ASTF16 数据表(PDF) 63 Page - Analog Devices

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