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ADE7169ASTF16 数据表(PDF) 92 Page - Analog Devices |
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ADE7169ASTF16 数据表(HTML) 92 Page - Analog Devices |
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92 / 140 page  ADE7169F16 Preliminary Technical Data Rev. PrD | Page 92 of 140 Table 80. LCD Data SFR (LCDDAT, 0xAE) Bit Location Bit Mnemonic Default Value Description 7-0 LCDDATA 0 Data to be written into or read out of the LCD Memory SFRs. Table 81. LCD Segment Enable 2 SFR (LCDSEGE2, 0xED) Bit Location Bit Mnemonic Default Value Description 7-4 RESERVED 0 Reserved FP19 Function Select bit 0 General Purpose I/O 3 FP19EN 0 1 LCD Function FP18 Function Select bit 0 General Purpose I/O 2 FP18EN 0 1 LCD Function FP17 Function Select bit 0 General Purpose I/O 1 FP17EN 0 1 LCD Function FP16 Function Select bit 0 General Purpose I/O 0 FP16EN 0 1 LCD Function LCD SETUP The LCD Configuration SFR (LCDCON, 0x95) configures the LCD module to drive the type of LCD in the user end system. The BIAS and LMUX[1:0] bits in this SFR should be set according to the LCD specifications. The COM2/FP28 and COM3/FP27 pins default to LCD segment lines. Selecting the 3x multiplex level in the LCD Configuration SFR (LCDCON, 0x95) by setting LMUX[1:0] to 2d, changes the FP28 pin functionality to COM2. The 4x multiplex level selection, LMUX[1:0]=3d, changes the FP28 pin to COM2 and the FP27 pin to COM3. LCD segments FP0-FP15 are enabled by default. Additional pins are selected for LCD functionality in the LCD Segment Enable SFR (LCDSEGE, 0x97) and LCD Segment Enable 2 SFR (LCDSEGE2, 0xED) where there are individual enable bits for segment pins FP16-25. The LCD pins do not have to be enabled sequentially. For example, if the alternate function of FP23, the timer 2 input, is required, then any of the other shared pins, FP16-25, could be enabled instead. The Display Element Control section contains details about setting up the LCD data memory to turn individual LCD segments ON and OFF. Setting the LCDRST bit in the LCD Configuration SFR (LCDCON, 0x95) will reset the LCD data memory to its default, zero. A power on reset also clears the LCD data memory. LCD TIMING AND WAVEFORMS An LCD segment acts like a capacitor that is charged and discharged at a certain rate. The rate at which these capacitors are charged and discharged, the refresh rate, determines the visual characteristics of the LCD. A slow refresh rate will result in the user being able to see the LCD blink on and off in between refreshes. A fast refresh rate will present a screen that appears to be lit up continuously. However, a faster refresh rate consumes more power. The frame rate, or refresh rate, for the LCD module is derived from the LCD clock, fLCDCLK. The LCD clock is selected as 2048Hz or 128Hz by the CLKSEL bit in the LCD Configuration X SFR (LCDCONX, 0x9C). The minimum refresh rate that is needed for the LCD to appear solid, without blinking, is independent of the multiplex level. The LCD waveform frequency, fLCD, is the frequency at which the LCD switches which common line is active. Thus the LCD waveform frequency depends heavily on the multiplex level. The frame rate and LCD waveform frequency are set by fLCDCLK, the multiplex level and the FD[3:0] frame rate selection bits in the LCD Clock SFR (LCDCLK, 0x96). The LCD module provides 16 different frame rates for fLCDCLK=2048Hz, ranging from 8 to 128Hz for an LCD with 4x multiplexing. There are fewer options available with fLCDCLK=128Hz, ranging from 8 to 32Hz for a 4x multiplexed |
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