ADE7169ASTF16 datasheet(59/140 Pages) AD

59 / 140 page

Preliminary Technical Data

ADE7169F16

Rev. PrD | Page 59 of 140

energy register is divided by 1. VARDIV is an 8-bit unsigned

accumulated in a 49-bit internal energy accumulation register.

The upper 24 bits of this register are accessible through a read

to the reactive energy register (VARHR[23:0]). A read to the

RVARHR register returns the content of the VARHR register

and the upper 24 bits of the internal register are cleared. As

shown in Figure 45, the reactive power signal is accumulated in

an internal 49-bit signed register. The reactive power signal can

be read from the waveform register by setting the WAVMODE

Enable Register 3 SFR (MIRQENH, 0xDB). Like the current

and voltage channels waveform sampling modes, the waveform

date is available at sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or

3.5 kSPS.

Figure 40 shows this energy accumulation for full-scale signals

(sinusoidal) on the analog inputs. These curves also apply for

the reactive energy accumulation

Note that the energy register contents rolls over to full-scale

negative (0x800000) and continues to increase in value when

the power or energy flow is positive. Conversely, if the power is

negative, the energy register underflows to full-scale positive

(0x7FFFFF) and continues to decrease in value.

By using the interrupt enable register, the ADE7169F16 can be

configured to issue an ADE interrupt to the 8052 core when the

reactive energy register is half-full (positive or negative) or

when an overflow or underflow occurs.

Integration time under steady Load

As mentioned in the active energy section, the discrete time

sample period (T) for the accumulation register is 1.22 μs

(5/CLKIN). With full-scale sinusoidal signals on the analog

inputs and the VARGAIN and VARDIV registers set to 0x000,

the integration time before the reactive energy register

overflows is calculated as follows:

Time =

xCCCCD

FFFF

FFFF,

xFFFF,

× 1.22 μs = 409.6 s = 6.82 min(15)

When VARDIV is set to a value different from 0, the integration

time varies, as shown in Equation 16.

VARDIV

Time

WDIV

= 0

(16)

Reactive energy accumulation modes

VAR signed accumulation mode

The ADE7169F16 reactive energy default accumulation mode is

a signed accumulation based on the reactive power information.

VAR anti-tamper accumulation mode

The ADE7169F16 is placed in VAR anti-tamper accumulation

mode by setting the SAVARM bit in the ACCMODE register

(0x0F). In this mode, the reactive power is accumulated

depending on the sign of the active power. When active power

is positive, the reactive power is added as it is to the reactive

energy register. When active power is negative, the reactive

power is subtracted to the reactive energy accumulator – see

Figure 46. The CF pulse also reflects this accumulation method

when in this mode. The default setting for this mode is off.

Transitions in the direction of power flow, and no-load

threshold are active in this mode.

POS

INTERRUPT STATUS REGISTERS

NEG

APSIGN Flag

NO-LOAD

THRESHOLD

ACTIVE POWER

NO-LOAD

THRESHOLD

REACTIVE ENERGY

NO-LOAD

THRESHOLD

REACTIVE POWER

NO-LOAD

THRESHOLD

Figure 46. Reactive Energy Accumulation in Anti-tamper Accumulation Mode

VAR absolute accumulation mode

The ADE7169F16 is placed in absolute accumulation mode by

setting the ABSVARM bit in the ACCMODE register (0x0F). In

absolute accumulation mode, the reactive energy accumulation

is done using the absolute reactive power, ignoring any

occurrence of power below the no-load threshold, as shown in

Figure 42 for the active energy. The CF pulse also reflects this

accumulation method when in this mode. The default setting

for this mode is off. Transitions in the direction of power flow,

and no-load threshold are active in this mode.

ADE7169ASTF16 数据表(PDF) 59 Page - Analog Devices

ADE7169ASTF16 数据表(HTML) 59 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ADE7169ASTF16 数据表(PDF) 59 Page - Analog Devices

ADE7169ASTF16 数据表(HTML) 59 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载