ADE7169ASTF16 datasheet(85/140 Pages) AD

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Preliminary Technical Data

ADE7169F16

Rev. PrD | Page 85 of 140

Table 67. Interrupt Flags

Interrupt Source

Flags

Bit

Address

Details

IE0

TCON.1

IE0

External Interrupt 0

TF0

TCON.5

TF0

Timer 0

IE1

TCON.3

IE1

External Interrupt 1

TF1

TCON.7

TF1

Timer 1

SCON.1

Transmit Interrupt

RI + TI

SCON.0

Receive Interrupt

T2CON.7

TF2

Timer 2 overflow flag

TF2 + EXF2

T2CON.6

EXF2

Timer 2 external flag

ITEMP (Temperature

ADC)

The Temperature ADC interrupt does not have an interrupt flag associated with it.

IPSM (Power

Supply)

IPSMF.6

FPSM

PSM interrupt flag

IADE (Energy

Measurement DSP)

MIRQSTL.7

Read MIRQSTH, MIRQSTM, MIRQSTL. If the AUTOCLR bit in the IPSME SFR is set, each

of these bytes will be reset after they are read. This is done on a per byte basis.

Reading MIRQSTH reads and clears only MIRQSTH.

Table 68. Status Flags

Interrupt Source

Flags

Bit

Address

Details

ITEMP (Temperature ADC)

The Temperature ADC interrupt does not have an status flag associated with it.

SPI2CSTAT

SPI Interrupt Status register

ISPI/I2CI

SPI2CSTAT

I2C Interrupt Status register

TIMECON.7

RTC Midnight flag

IRTC (RTC Interval Timer)

TIMECON.2

RTC Alarm flag

WDT (Watchdog Timer)

WDCON.2

WDS

Watchdog Timeout flag

A functional block diagram of the interrupt system is shown in

Figure 62. Note that the PSM interrupt is the only interrupt in

the highest priority level.

If an external wakeup event occurs to wake the ADE7169F16

from PSM2, a pending external interrupt will be generated.

When the EX0 or EX1 bits are set in the Interrupt Enable SFR

(IE, 0xA8) to enable external interrupts, the program counter

will be loaded with the IE0 or IE1 interrupt vector. The IE0 and

IE1 interrupt flags in the TCON register will not be affected by

events that occur when the 8052 MCU core is shut down during

PSM2 — see the Power Supply Monitor Interrupt (PSM)

section.

The RTC, temperature ADC and I2C/SPI interrupts are latched

such that pending interrupts cannot be cleared without entering

their respective interrupt service routines. Clearing the RTC

Midnight and Alarm flags will not clear a pending RTC

interrupt. Similarly, clearing the I2C/SPI status bits in the SPI

Interrupt Status Register SFR (SPISTAT, 0xEA) will not cancel a

pending I2C/SPI interrupt. These interrupts will remain

pending until the RTC or I2C/SPI interrupt vectors are enabled.

Their respective interrupt service routines will be entered

shortly thereafter.

Figure 62 shows how the interrupts are cleared when the

interrupt service routines are entered. Some interrupts with

multiple interrupt sources are not automatically cleared,

specifically the PSM, ADE, UART and Timer 2 interrupt

vectors. Note that the INT0 and INT1 interrupts are only

cleared if the external interrupt is configured to be triggered by

a falling edge, by setting IT0 in the Timer/Counter 0 and 1

Control SFR (TCON, 0x88). If INT0 or INT1 is configured to

interrupt on a low level, the interrupt service routine will be

reentered until the respective pin goes high.

ADE7169ASTF16 数据表(PDF) 85 Page - Analog Devices

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