ADE7169ASTF16 datasheet(93/140 Pages) AD

93 / 140 page

Preliminary Technical Data

ADE7169F16

Rev. PrD | Page 93 of 140

LCD. The 128Hz clock is beneficial for battery operation

because it consumes less power than the 2048Hz clock. The

frame rate is set by the FD[3:0] bits in the LCD Clock SFR

(LCDCLK, 0x96)—see Table 76 and Table 77.

The LCD waveform is inverted at twice the LCD waveform

frequency, fLCD. This way each frame has an average DC offset of

zero. ADC offset would degrade the lifetime and performance

of the LCD.

BLINK MODE

Blink mode is enabled by setting the BLINKEN bit in the LCD

Configuration SFR (LCDCON, 0x95). This mode is used to

alternate between LCD on and off states so that the LCD screen

appears to blink. There are two blinking modes: a software

controlled blink mode and an automatic blink mode.

Software Controlled Blink Mode

The LCD blink rate can be controlled by user code with the

BLKMOD[1:0] bits in the LCD Clock SFR (LCDCLK, 0x96) by

toggling the bits to turn the display on and off at a rate

determined by the MCU code.

Automatic Blink Mode

There are five blink rates available if the RTC peripheral is

enabled (enable the RTC by…xxx). These blink rates are

selected by the BLKMOD[1:0] and BLKFREQ[1:0] bits in the

LCD Clock SFR (LCDCLK, 0x96) – see Table 75.

DISPLAY ELEMENT CONTROL

A bank of 15 bytes of data memory located in the LCD module

controls the on or off state of each segment of the LCD. The

LCD data memory is stored in addresses 0 through 14 in the

LCD module. Each byte configures the on and off states of two

segment lines. The LSBs store the state of the even numbered

segment lines and the MSBs store the state of the odd numbered

segment lines. For example, LCD data address zero refers to

segment lines one and zero—see Table 82. Note that the LCD

data memory is maintained in the PSM2 operating mode.

Table 82. LCD Data Memory accessed indirectly through

LCD Pointer SFR (LCDPTR, 0xAC) and LCD Data SFR

(LCDDAT, 0xAE)

LCD Memory

Address

COM3

COM2

COM1

COM0

COM3

COM2

COM1

COM0

0Eh

FP28

0Dh

FP27

FP26

0Ch

FP25

FP24

0Bh

FP23

FP22

0Ah

FP21

FP20

09h

FP19

FP18

08h

FP17

FP16

07h

FP15

FP14

06h

FP13

FP12

05h

FP11

FP10

04h

FP9

FP8

03h

FP7

FP6

02h

FP5

FP4

01h

FP3

FP2

00h

FP1

FP0

COM# designates the common lines

FP# designates the segment lines

The LCD data memory is accessed indirectly through the LCD

Pointer SFR (LCDPTR, 0xAC)and Table 80. LCD Data SFR

(LCDDAT, 0xAE). Moving a value to the LCD Pointer SFR

(LCDPTR, 0xAC) selects the LCD data byte to be accessed and

initiates a read or write operation—see Table 79.

Writing to LCD Data registers

To update the LCD data memory, first set the LSB of the LCD

Configuration Y SFR (LCDCONY, 0xB1) to freeze the data

being displayed on the LCD while updating it. Then, move the

data to the LCD Data SFR (LCDDAT, 0xAE) prior to accessing

the LCD Pointer SFR (LCDPTR, 0xAC). When the MSB of the

LCD Pointer SFR (LCDPTR, 0xAC) is set, the content of the

LCD Data SFR (LCDDAT, 0xAE) is transferred to the internal

LCD data memory designated by the address in the LCD

Pointer SFR (LCDPTR, 0xAC). Clear the LSB of the LCD

Configuration Y SFR (LCDCONY, 0xB1) when all of the data

memory has been updated to allow to use the new LCD set up

for display.

Sample 8052 code to update the segments attached to pins FP10

and FP11 on is shown below:

ORL

LCDCONY,#01h

; start updating the data

MOV

LCDDATA,#FFh

MOV

LCDPTR,#80h OR 05h

ANL

LCDCONY,#0FEh ; update finished

Reading LCD Data registers

When the MSB of the LCD Pointer SFR (LCDPTR, 0xAC) is

cleared, the content of the LCD Data memory address

designated by LCDPTR are transferred to the LCD Data SFR

(LCDDAT, 0xAE).

Sample 8052 code to read the contents of LCD data memory

address 07h, which holds the on and off state of the segments

attached to FP14 and FP15, is shown below:

MOV

LCDPTR,#NOT 80h AND 07h

MOV

R1, LCDDATA

VOLTAGE GENERATION

The ADE7169F16 provides two ways to generate the LCD

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