ADE7169ASTF16 datasheet(26/140 Pages) AD

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ADE7169F16

Preliminary Technical Data

Rev. PrD | Page 26 of 140

VSWOUT output pin reflects the voltage at VSW, and has a

maximum output current of TBD mA. This pin may also be

used to power a limited number of peripheral components. The

2.5V analog supply, VINTA and the 2.5V supply for the core logic,

VINTD, are derived by on-chip linear regulators from VSW. Figure

9 shows the power supply architecture of ADE7169F16.

The ADE7169F16 provides automatic battery switchover

between VDD and VBAT based on the voltage level detected at VDD

or VDCIN. Additionally, the BCTRL input can also be used to

trigger a battery switchover. The conditions for switching VSW

from VDD to VBAT and back to VDD are described in the Battery

Switchover section.

VDCIN is an input pin that can be connected to a 0V to 3.3V DC

signal. This input is intended for power supply supervisory

purposes and does not provide power to the ADE7169F16

circuitry - see Battery Switchover section.

MCU

SCRATCHPAD

LCD

RTC

TEMPERATURE ADC

DCIN

INTD

INTA

3.3V

2.5V

LDO

BAT

SWOUT

BCTRL

ADE

SPI/I2C

UART

LDO

POWER SUPPLY

MANAGEMENT

ADC

Figure 9: Power Supply Architecture

BATTERY SWITCHOVER

ADE7169F16 monitors VDD, VBAT, and VDCIN. Automatic

battery switchover from VDD to VBAT can be configured based on

the status of VDD, VDCIN, or the BCTRL pin. Battery switchover is

enabled by default. Setting bit 1 in the Battery Switchover

Configuration SFR (BATPR, 0xF5), disables battery switchover

so that VDD is always connected to VSW. The source of VSW is

indicated by bit 6 in the Peripheral Configuration SFR

(PERIPH, 0xF4), which is set when VSW is connected to VDD and

cleared when VSW is connected to VBAT.

The battery switchover functionality provided by the

ADE7169F16 allows a seamless transition from VDD to VBAT. An

automatic battery switchover option ensures a stable power

supply to the ADE7169F16, as long as the external battery

voltage is above TBD V. It allows continuous code execution

even while the internal power supply is switching from VDD to

VBAT and back. Note that the energy metering ADCs are not

available when VBAT is being used for VSW.

Power supply monitor (PSM) interrupts can be enabled to

indicate when battery switchover occurs and when the VDD

power supply is restored - see the Power Supply Monitor

Interrupt (PSM) section.

Switching from VDD to VBAT

There are three events that can be enabled to switch the internal

power supply, VSW, from VDD to VBAT:

(VDCIN < 1.2 V):

When VDCIN falls below 1.2V VSW

switches from VDD to VBAT. This event is enabled

when the BATTPROG[1:0] bits in the Battery

Switchover Configuration SFR (BATPR, 0xF5) are

clear. Setting this bit will disable switchover based on

VDCIN. Battery switchover on low VDCIN is disabled by

default.

(VDD < TBD V):

When VDD falls below TBD V VSW

switches from VDD to VBAT. This event is enabled

when BATTPROG[1] in the Battery Switchover

Configuration SFR (BATPR, 0xF5) is cleared.

Rising edge on BCTRL:

When the battery control

pin, BCTRL, goes high, VSW switches from VDD to

VBAT. This external switchover signal can trigger a

switchover to VBAT at any time. Setting bits

INT1PRG[4:2] to 0bx01 in the Interrupt pins

configuration SFR (INTPR, 0xFF) enables the battery

control pin.

Switching from VBAT to VDD

To switch VSW back from VBAT to VDD all of the events that are

enabled to force battery switchover must be false:

(VDCIN < 1.2 V) and (VDD < TBD V) Enabled:

If the

low VDCIN condition is enabled, VSW switches to VDD

after VDCIN remains above TBD V for TBD seconds

and VDD remains above TBD V for TBD seconds.

(VDD < TBD V) Enabled:

VSW switches back to VDD

after VDD has been above TBD V for TBD seconds.

BCTRL Enabled:

VSW switches back to VDD after

BCTRL is low and number 1 or number 2 are satisfied.

POWER SUPPLY MONITOR INTERRUPT (PSM)

The Power Supply Monitor Interrupt (PSM) alerts the 8052 core

of power supply events. The PSM interrupt is disabled by

default. Setting the EPSM bit in the Interrupt Enable and

Priority 2 SFR (IEIP2, 0xA9) enables the PSM interrupt. The

Power Management Interrupt Enable SFR (IPSME, 0xEC)

controls the events that result in a PSM interrupt. Figure 10 is a

diagram illustrating how the PSM interrupt vector is shared

among the PSM interrupt sources. The PSM interrupt flags are

latched and must be cleared by writing to the flag register.

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