ADE7169ASTF16 datasheet(60/140 Pages) AD

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ADE7169F16

Preliminary Technical Data

Rev. PrD | Page 60 of 140

REACTIVE ENERGY

NO-LOAD

THRESHOLD

REACTIVE POWER

NO-LOAD

THRESHOLD

Figure 47. Reactive Energy Accumulation in Absolute Accumulation Mode

Reactive energy Pulse output

ADE7169F16 also provides all the circuitry to have a pulse

output those frequency is proportional to reactive power – see

Energy-to-Frequency Conversion section. This pulse frequency

output uses the calibrated signal after VARGAIN and its

behavior is consistent with the setting of the reactive energy

accumulation mode in the ACCMODE register (0x0F). The

pulse output is active low and should be preferably connected to

an LED as shown on Figure 53.

Line cycle reactive energy accumulation mode

In line cycle energy accumulation mode, the energy accumula-

tion of the ADE7169F16 can be synchronized to the voltage

channel zero crossing so that reactive energy can be

accumulated over an integral number of half line cycles. The

advantage of this mode is similar to the ones explained in the

Active energy Line cycle accumulation mode – see Line cycle

active energy accumulation mode section. In line cycle energy

accumulation mode, the ADE7169F16 accumulates the reactive

power signal in the LVARHR register for an integral number of

line cycles, as shown in Figure 48. The number of half line

cycles is specified in the LINCYC register. The ADE7169F16

can accumulate active power for up to 65,535 half line cycles.

Because the reactive power is integrated on an integral number

of line cycles, at the end of a line cycle energy accumulation

cycle the CYCEND flag in the Interrupt Status Register 3 SFR

(MIRQSTH, 0xDE). If the CYCEND enable bit in the Interrupt

Enable Register 3 SFR (MIRQENH, 0xDB) is set, the 8052 core

has a pending ADE interrupt. The ADE interrupt stays active

until the CYCEND status bit is cleared—see Energy

measurement interrupts section. Another calibration cycle will

start as soon as the CYCEND flag is set. If the LVARHR register

is not read before a new CYCEND flag is set, the LVARHR

As for LWATTHR, when a new half line cycles is written in

LINCYC register, the LVARHR register is reset and a new

accumulation start at the next zero-crossing. The number of

half line cycles is then counted until LINCY is reached. This

implementation provides a valid measurement at the first

CYCEND interrupt after writing to the LINCYC register. The

line reactive energy accumulation uses the same signal path as

the reactive energy accumulation. The LSB size of these two

registers is equivalent.

VARDIV[7:0]

VAROS[15:0]

VARGAIN[11:0]

LPF1

LVARHR [23:0]

ACCUMULATE REACTIVE

ENERGY IN INTERNAL

THE LVARHR REGISTER

AT THE END OF LINCYC

HALF LINE CYCLES

OUTPUT

FROM

LPF2

FROM VOLTAGE

CHANNEL

ADC

LINCYC [15:0]

ZERO CROSS

DETECTION

CALIBRATION

CONTROL

DIGITAL TO FREQUENCY

CONVERTER

Figure 48 Line Cycle . Reactive Energy Accumulation Mode

APPARENT POWER CALCULATION

The apparent power is defined as the maximum power that can

be delivered to a load. Vrms and Irms are the effective voltage and

current delivered to the load; the apparent power (AP) is defined

ADE7169ASTF16 数据表(PDF) 60 Page - Analog Devices

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