ADE7169ASTF16 datasheet(62/140 Pages) AD

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ADE7169F16

Preliminary Technical Data

Rev. PrD | Page 62 of 140

VADIV

APPARENT POWER

VAHR[23:0]

APPARENT POWER ARE

ACCUMULATED (INTEGRATED) IN

THE APPARENT ENERGY REGISTER

TIME (nT)

APPARENT POWER

SIGNAL = P

Figure 50. ADE7169F16 Apparent Energy Calculation

Note that the apparent energy register is unsigned. By setting the

VAEHF and VAEOF bits in the Interrupt Enable Register 2 SFR

(MIRQENM, 0xDA), the ADE7169F16 can be configured to

issue an ADE interrupt to the 8052 core when the apparent

energy register is half full or when an overflow occurs. The half

full interrupt for the unsigned apparent energy register is based

on 24 bits as opposed to 23 bits for the signed active energy

Integration Times under Steady Load

As mentioned in the last section, the discrete time sample

period (T) for the accumulation register is 1.22 μs (5/MCLK).

With full-scale sinusoidal signals on the analog inputs and the

VAGAIN register set to 0x000, the average word value from

apparent power stage is 0x1A36E2—see the section. The

maximum value that can be stored in the apparent energy

word value is added to the internal register, which can store 248

or 0xFFFF,FFFF,FFFF before it overflows. Therefore, the

integration time under these conditions with VADIV = 0 is

calculated as follows:

Time =

055

FFFF

FFFF,

xFFFF,

× 1.22 μs = 199 s = 3.33 min (32)

When VADIV is set to a value different from 0, the integration

time varies, as shown in Equation 33.

Time = TimeWDIV = 0 × VADIV

(33)

Apparent energy Pulse output

ADE7169F16 also provides all the circuitry to have a pulse

output those frequency is proportional to apparent power – see

Energy-to-Frequency Conversion section. This pulse frequency

output uses the calibrated signal after VAGAIN. This output can

also be used to output a pulse those frequency is proportional to

Irms.

The pulse output is active low and should be preferably

connected to an LED as shown on Figure 53.

Line Apparent Energy Accumulation

The ADE7169F16 is designed with a special apparent energy

accumulation mode, which simplifies the calibration process.

By using the on-chip zero-crossing detection, the ADE7169F16

accumulates the apparent power signal in the LVAHR register

for an integral number of half cycles, as shown in Figure 51. The

line apparent energy accumulation mode is always active.

The number of half line cycles is specified in the LINCYC

can accumulate apparent power for up to 65535 combined half

cycles. Because the apparent power is integrated on the same

integral number of line cycles as the line active and reactive

energy register, these values can be compared easily. The

energies are calculated more accurately because of this precise

timing control and provide all the information needed for

reactive power and power factor calculation. At the end of an

energy calibration cycle, the CYCEND flag in the Interrupt

Status Register 3 SFR (MIRQSTH, 0xDE) is set. If the CYCEND

enable bit in the Interrupt Enable Register 3 SFR (MIRQENH,

0xDB) is enabled, the 8052 core has a pending ADE interrupt.

As for LWATTHR, when a new half line cycles is written in

LINECYC register, the LVAHR register is reset and a new

accumulation start at the next zero-crossing. The number of

half line cycles is then counted until LINCY is reached. This

implementation provides a valid measurement at the first

CYCEND interrupt after writing to the LINCYC register. The

line apparent energy accumulation uses the same signal path as

the apparent energy accumulation. The LSB size of these two

registers is equivalent.

ADE7169ASTF16 数据表(PDF) 62 Page - Analog Devices

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