ADE7169ASTF16 datasheet(126/140 Pages) AD

126 / 140 page

ADE7169F16

Preliminary Technical Data

Rev. PrD | Page 126 of 140

SPITxBF

Status bit for SPI Tx buffer. When set, the SPI Tx buffer is full.

SPI PINS

MISO (Master In, Slave Out Data I/O Pin)

The MISO pin is configured as an input line in master mode

and as an output line in slave mode. The MISO line on the

master (data in) should be connected to the MISO line in the

slave device (data out).The data is transferred as byte-wide (8-

bit) serial data, MSB first.

MOSI (Master Out, Slave In Pin)

The MOSI pin is configured as an output line in master mode

and as an input line in slave mode. The MOSI line on the

master (data out) should be connected to the MOSI line in the

slave device (data in).The data is transferred as byte-wide (8-

bit) serial data, MSB first.

SCLK (Serial Clock I/O Pin)

The master serial clock (SCLK) is used to synchronize the data

being transmitted and received through the MOSI and MISO

data lines. The SCLK pin is configured as an output in master

mode and as an input in slave mode.

In master mode, the bit rate, polarity, and phase of the clock are

controlled by the SPI Configuration Register SFR (SPIMOD1,

0xE8)

and SPI Configuration Register SFR (SPIMOD2, 0xE9).

In slave mode, the SPI Configuration Register SFR (SPIMOD2,

0xE9)

must be configured with the phase and polarity of the

expected input clock.

In both master and slave modes, the data is transmitted on one

edge of the SCLK signal and sampled on the other. It is

important, therefore, that CPHA and CPOL are configured the

same for the master and slave devices.

SS (Slave Select Pin)

In SPI slave mode, a transfer is initiated by the assertion of SS

low. The SPI port will then transmit and receive 8-bit data until

the data is concluded by deassertion of SS. In slave mode, SS is

always an input.

In SPI master mode, the SS can be used to control data transfer

to a slave device. In the automatic slave select control mode, the

SS is asserted low to select the slave device and then raised to

deselect the slave device after the transfer is complete.

Automatic slave select control is enabled by setting the

AUTO_SS bit in the SPI Configuration Register SFR (SPIMOD1,

0xE8)

In a multi-master system, the SS can be configured as an input

so that the SPI peripheral can operate as a slave in some

situations and as a master in other situations. In this case, the

slave selects for the slaves controlled by this SPI peripheral

should be generated with general I/O pins.

SPI MASTER OPERATING MODES

The double buffered receive and transmit registers can be used

to maximize the throughput of the SPI peripheral by

continuously streaming out data in master mode. The

continuous transmit mode is designed to use the full capacity

of the SPI. In this mode, the master will transmit and receive

data until the SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A)

mode is enabled by setting the SPICONT bit in the SPI

Configuration Register SFR (SPIMOD2, 0xE9)

.The SPI peripheral

also offers a single byte read and a single byte write function.

In master mode, the type of transfer is handled automatically

depending on the configuration of bits 0 and 7 of the SPI

Configuration Register SFR (SPIMOD2, 0xE9)

. Table 127 shows

the sequence of events that should be performed for each

master operating mode. Based on the SS configuration, some of

these events will take place automatically.

Table 127. Procedures for using SPI as a Master

Mode

SPIMOD[7]

= SPICONT

bit

SPIMOD[0]

= TIMODE

Description of operation

Step1: Read SPIRx SFR

Step2: SS is asserted low and read routine is initiated

Step 3: SPIRxIRQ Interrupt flag is set when the SPIRx SFR is full

Step 4: SS is deasserted high

Single Byte

Read

Step 5: Read SPIRx SFR to clear SPIRxIRQ Interrupt flag

Step 1: Write to SPITx SFR

Step 2: SS is asserted low and write routine is initiated

Step 3: SPITxIRQ Interrupt Flag is set when SPITx register is empty

Step 4: SS is deasserted high

Single Byte

Write

Step 5: Write to SPITx SFR to clear SPITxIRQ Interrupt flag

ADE7169ASTF16 数据表(PDF) 126 Page - Analog Devices

ADE7169ASTF16 数据表(HTML) 126 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载