VL6524 datasheet(63/70 Pages) STMICROELECTRONICS

部件名	VL6524

功能描述	VGA single-chip camera module

PDF	70 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

标志

63 / 70 page

VL6524/VS6524

Electrical characteristics

63/70

13.4.4

Parallel data interface timing

VL6524/VS6524 contains a parallel data output port (D[7:0]) and associated qualification

signals (HSYNC, VSYNC, PCLK and FSO).

This port can be enabled and disabled (tri-stated) to facilitate multiple camera systems or

bit-serial output configurations. The port is disabled (high impedance) upon reset.

Figure 35.

Parallel data output video timing

13.5

ESD handling characteristics

Table 39.

Parallel data interface timings

Symbol

Description

Conditions

Min.

Typ.

Max.

Unit

fPCLK

PCLK frequency

MHz

tPCLKL

PCLK low width

tPCLKH

PCLK high width

tDV

PCLK to output valid

-5

tPCLKL

tPCLKH

1/fPCLK

PCLK

D[0:7]

HSYNC

polarity = 0

tDV

Valid

VSYNC

Table 40.

ESD handling characteristics

Test

Criteria

Unit

ESD Machine Model

150

ESD Human body

1.5

VL6524 数据表(PDF) 63 Page - STMicroelectronics

VL6524 数据表(HTML) 63 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

数据表下载