VL6524 datasheet(31/70 Pages) STMICROELECTRONICS

31 / 70 page

VL6524/VS6524

Getting started

31/70

Getting started

9.1

Initial power up

Before any communication is possible with the VL6524/VS6524 the following steps must

take place:

Apply VDD (1.8V or 2.8V)

Apply AVDD (2.8V)

Apply an external CLOCK (6.5 MHz to 26 MHz)

Assert CE line HIGH

These steps can all take place simultaneously. After these steps are complete a delay of

200 µs is required before any I²C communication can take place, see

Figure 3: Power up

sequence.

9.2

Minimum startup command sequence

Enable the microprocessor - before any commands can be sent to the

VL6524/VS6524, the internal microprocessor must be enabled by writing the value

0x06 to the

MicroEnable register 0xC003 (Table 7: Low-level control registers).

Enable the digital I/O - after power up the digital I/O of the VL6524/VS6524 is in a high-

impedance state (‘tri-state’). The I/O are enabled by writing the value 0x01 to the

Enable I/O register 0xC034 (Table 7: Low-level control registers).

The user can then program the system clock frequency and setup the required output

format before placing the VL6524/VS6524 in RUN mode by writing 0x02 to the

bUserCommand register 0x0180 (Table 9: Mode control).

The above three commands represent the absolute minimum required to get video data

output.

The default configuration results in an output of VGA, 30 fps, YUV data format with ITU

embedded codes requiring a external clock frequency of 12MHz.

In practice the user is likely to require to write some additional setup information prior to

receive the required data output.

VL6524 数据表(PDF) 31 Page - STMicroelectronics