VL6524 datasheet(10/70 Pages) STMICROELECTRONICS

10 / 70 page

System architecture

VL6524/VS6524

10/70

System architecture

The VL6524/VS6524 consists of the following main blocks:

●

VGA-sized pixel array

●

Video timing generator

●

Video pipe

●

Statistics gathering unit

●

Clock generator

●

Microprocessor

A simplified block diagram is shown in

Figure 1.

VL6524/VS6524 simplified block diagram

3.1

Operation

A video timing generator controls a VGA-sized pixel array to produce raw images at up to 30

frames per second. The analogue pixel information is digitized and passed into the video

pipe. The video pipe contains a number of different functions (explained in detail later). At

the end of the video pipe data is output to the host system over an 8-bit parallel interface

along with qualification signals.

Microprocessor

SDA

SCL

AVDD

HSYNC

PCLK

D[0:7]

CLK

VSYNC

Clock

generator

I²C

Statistics

Gathering

Video timing

generator

Reset

VREG

VDD

I²C Interface

FSO

GND

VGA

Pixel array

Video pipe

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