MPC8560CPXAPDB datasheet(24/108 Pages) FREESCALE

部件名	MPC8560CPXAPDB

功能描述	Integrated Processor Hardware Specifications

PDF	108 Pages

Scroll/Zoom	100%

制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

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MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1

Freescale Semiconductor

DDR SDRAM

6.2.2.2 Load Effects on Address/Command Bus

Table 17 provides approximate delay information that can be expected for the address and command signals of the

DDR controller for various loadings. These numbers are the result of simulations for one topology. The delay

numbers will strongly depend on the topology used. These delay numbers show the total delay for the address and

command to arrive at the DRAM devices. The actual delay could be different than the delays seen in simulation,

depending on the system topology. If a heavily loaded system is used, the DLL loop may need to be adjusted to meet

setup requirements at the DRAM.

Table 17. Expected Delays for Address/Command

Load

Delay

Unit

4 devices (12 pF)

3.0

9 devices (27 pF)

3.6

36 devices (108 pF) + 40 pF compensation capacitor

5.0

36 devices (108 pF) + 80 pF compensation capacitor

5.2

MPC8560CPXAPDB 数据表(PDF) 24 Page - Freescale Semiconductor, Inc