MPC8560CPXAPDB datasheet(5/108 Pages) FREESCALE

5 / 108 page

MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Overview

— Supports four priority levels (ordering within a level)

— Reordering across priority levels

— Maximum data payload of 256 bytes per packet

— Packet pacing support at the physical layer

— CRC protection for packets

— Supports atomic operations increment, decrement, set, and clear

— LVDS signaling

•

RapidIO–compliant message unit

— One inbound data message structure (inbox)

— One outbound data message structure (outbox)

— Supports chaining and direct modes in the outbox

— Support of up to 16 packets per message

— Support of up to 256 bytes per packet and up to 4 Kbytes of data per message

— Supports one inbound doorbell message structure

•

Programmable interrupt controller (PIC)

— Programming model is compliant with the OpenPIC architecture

— Supports 16 programmable interrupt and processor task priority levels

— Supports 12 discrete external interrupts

— Supports 4 message interrupts with 32-bit messages

— Supports connection of an external interrupt controller such as the 8259 programmable interrupt

controller

— Four global high resolution timers/counters that can generate interrupts

— Supports 22 other internal interrupt sources

— Supports fully nested interrupt delivery

— Interrupts can be routed to external pin for external processing

— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs

— Interrupt summary registers allow fast identification of interrupt source

•I2C controller

— Two-wire interface

— Multiple master support

— Master or slave I2C mode support

— On-chip digital filtering rejects spikes on the bus

•

Boot sequencer

— Optionally loads configuration data from serial ROM at reset via the I2C interface

— Can be used to initialize configuration registers and/or memory

— Supports extended I2C addressing mode

— Data integrity checked with preamble signature and CRC

•

Local bus controller (LBC)

— Multiplexed 32-bit address and data operating at up to 166 MHz

— Eight chip selects support eight external slaves

MPC8560CPXAPDB 数据表(PDF) 5 Page - Freescale Semiconductor, Inc

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