MPC8560CPXAPDB datasheet(2/108 Pages) FREESCALE

2 / 108 page

MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Overview

Figure 1. MPC8560 Block Diagram

1.1 Key Features

The following lists an overview of the MPC8560 feature set.

•

High-performance, 32-bit Book E–enhanced core that implements the PowerPC architecture

— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked

entirely or on a per-line basis. Separate locking for instructions and data

— Memory management unit (MMU) especially designed for embedded applications

— Enhanced hardware and software debug support

— Performance monitor facility (similar to but different from the MPC8560 performance monitor

described in Chapter 18, “Performance Monitor.”

•

High-performance RISC CPM operating at up to 333 MHz

— CPM software compatibility with previous PowerQUICC families

— One instruction per clock

— Executes code from internal ROM or instruction RAM

— 32-bit RISC architecture

— Tuned for communication environments: instruction set supports CRC computation and bit

manipulation.

— Internal timer

I2C Controller

Local Bus Controller

RapidIO Controller

PCI Controller

DMA Controller

10/100/1000 MAC

MII, GMII, TBI,

RTBI, RGMIIs

Serial

DMA

ROM

I-Memory

DPRAM

RISC

Engine

Parallel I/O

Baud Rate

Generators

Timers

MCC

FCC

SCC

SPI

I2C

UTOPIAs

MIIs,

TDMs

I/Os

CPM

DDR SDRAM Controller

CPM

Controller

Interrupt

256KB

L2-Cache/

SRAM

e500 Core

32 KB L1

I Cache

32 KB L1

D Cache

Core Complex Bus

e500

Coherency

Module

OCeaN

16 Gb/s

RapidIO-8

133 MHz

PCI 64b

IRQs

SDRAM

DDR

GPIO

32b

Programmable

Interrupt Controller

MPHY

RMIIs

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