MPC8560CPXAPDB datasheet(84/108 Pages) FREESCALE

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MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Clocking

15 Clocking

This section describes the PLL configuration of the MPC8560. Note that the platform clock is identical to the CCB

clock.

15.1 Clock Ranges

Table 54 provides the clocking specifications for the processor core and Table 55 provides the clocking

specifications for the memory bus.

15.2 Platform/System PLL Ratio

The platform clock is the clock that drives the L2 cache, the DDR SDRAM data rate, and the e500 core complex

bus (CCB), and is also called the CCB clock. The values are determined by the binary value on LA[28:31] at power

up, as shown in Table 56.

There is no default for this PLL ratio; these signals must be pulled to the desired values.

Table 54. Processor Core Clocking Specifications

Characteristic

Maximum Processor Core Frequency

Unit

Notes

667 MHz

833 MHz

Min

Max

Min

Max

e500 core processor frequency

400

667

400

833

MHz

1, 2

Notes:

1.Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that

the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their

respective maximum or minimum operating frequencies. Refer to Section 15.2, “Platform/System

PLL Ratio,” and Section 15.3, “e500 Core PLL Ratio,” for ratio settings.

2.)The minimum e500 core frequency is based on the minimum platform frequency of 200 MHz.

Table 55. Memory Bus Clocking Specifications

Characteristic

Maximum Processor Core Frequency

Unit

Notes

667 MHz

833 MHz

Min

Max

Min

Max

Memory bus frequency

100

166

100

166

MHz

1, 2

Notes:

1.Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that

the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their

respective maximum or minimum operating frequencies. Refer to Section 15.2, “Platform/System

PLL Ratio,” and Section 15.3, “e500 Core PLL Ratio,” for ratio settings.

2.The memory bus speed is half of the DDR data rate, hence, half of the platform clock frequency.

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