MPC8560CPXAPDB datasheet(19/108 Pages) FREESCALE

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MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1

Freescale Semiconductor

RESET Initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements of the

MPC8560. Table 10 provides the RESET initialization AC timing specifications for the DDR SDRAM

component(s).

Table 11 provides the PLL and DLL lock times.

Table 10. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Notes

Required assertion time of HRESET

100

—

µs

Minimum assertion time for SRESET

512

—

SYSCLKs

PLL input setup time with stable SYSCLK before

HRESET negation

100

—

µs

Input setup time for POR configs (other than PLL

config) with respect to negation of HRESET

—

SYSCLKs

Input hold time for POR configs (including PLL config)

with respect to negation of HRESET

—

SYSCLKs

Maximum valid-to-high impedance time for actively

driven POR configs with respect to negation of

HRESET

—

SYSCLKs

Notes:

1.SYSCLK is identical to the PCI_CLK signal and is the primary clock input for the MPC8560. See the

MPC8560

PowerQUICC III™ Integrated Communications Processor Preliminary Reference Manual for more

details.

Table 11. PLL and DLL Lock Times

Parameter/Condition

Min

Max

Unit

Notes

PLL lock times

—

100

µs

DLL lock times

7680

122,880

CCB Clocks

1, 2

Notes:

1.DLL lock times are a function of the ratio between the output clock and the platform (or CCB) clock. A 2:1 ratio

results in the minimum and an 8:1 ratio results in the maximum.

2. The CCB clock is determined by the SYSCLK

× platform PLL ratio.

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