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MPC8560CPXAPDB 数据表(PDF) 49 Page - Freescale Semiconductor, Inc

部件名 MPC8560CPXAPDB
功能描述  Integrated Processor Hardware Specifications
PDF  108 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MPC8560CPXAPDB 数据表(HTML) 49 Page - Freescale Semiconductor, Inc

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MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1
Freescale Semiconductor
49
CPM
Table 35 shows CPM I2C AC Timing.
Figure 30 is a a diagram of CPM I2C Bus Timing.
Figure 30. CPM I2C Bus Timing Diagram
Table 35. CPM I2C AC Timing
Characteristic
Symbol
Min
Max
Unit
SCL clock frequency (slave)
fSCL
0
FMAX
1
Hz
SCL clock frequency (master)
fSCL
BRGCLK/16512
BRGCLK/48
Hz
Bus free time between transmissions
tSDHDL
1/(2.2 * fSCL)
-
s
Low period of SCL
tSCLCH
1/(2.2 * fSCL)
-
s
High period of SCL
tSCHCL
1/(2.2 * fSCL)
-
s
Start condition setup time 2
tSCHDL
2/(divider * fSCL)
-
s
Start condition hold time 2
tSDLCL
3/(divider * fSCL)
-
s
Data hold time 2
tSCLDX
2/(divider * fSCL)
-
s
Data setup time 2
tSDVCH
3/(divider * fSCL)
-
s
SDA/SCL rise time
tSRISE
-
1/(10 * fSCL)
s
SDA/SCL fall time
tSFALL
-
1/(33 * fSCL)
s
Stop condition setup time
tSCHDH
2/(divider * fSCL)
-
s
Notes:
1.FMAX = BRGCLK/(min_divider*prescaler). Where prescaler=25-I2MODE[PDIV]; and min_divider=12 if digital filter
disabled and 18 if enabled.
Example #1: if I2MODE[PDIV]=11 (prescaler=4) and I2MODE[FLT]=0 (digital filter disabled) then
FMAX=BRGCLK/48
Example #2: if I2MODE[PDIV]=00 (prescaler=32) and I2MODE[FLT]=1 (digital filter enabled) then
FMAX=BRGCLK/576
2.divider = fSCL/prescaler .
In master mode: divider=BRGCLK/(fSCL*prescaler)=2*(I2BRG[DIV]+3)
In slave mode: divider=BRGCLK/(fSCL*prescaler)
SCL
SDA
tSDHDL
tSCLCH
tSCHCL
tSCHDL
tSDLCL
tSCLDX
tSDVCH
tSRISE
tSFALL
tSCHDH



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