AD9983ASLASHPCB datasheet(27/44 Pages) AD

27 / 44 page

Preliminary Technical Data

AD9983A

Rev. PrA | Page 27 of 44

Hex

Address

Read/Write,

Read Only

Bits

Default

Value

Description

**** 0***

Power-Down.

0 = Normal operation

1 = Power-down

**** *0**

Power-Down Pin Polarity.

0 = Active low

1 = Active high

**** **0*

Power-Down Fast Switching Control.

0 = Normal power-down operation

1 = The chip stays powered up and the outputs are put in high

impedance mode

**** ***0

SOGOUT High Impedance Control.

0 = SOGOUT operates as normal during power-down

1 = SOGOUT is in high impedance during power-down

0x1F

R/W

7:5

100* ****

Output Select 1

Output Mode.

100 = 4:4:4 output mode

101 = 4:2:2 output mode

110 = 4:4:4—DDR output mode

***1 ****

Primary Output Enable.

0 = Primary output is in high impedance state

1 = Primary output is enabled

**** 0***

Secondary Output Enable.

0 = Secondary output is in high impedance state

1 = Secondary output is enabled

2:1

**** *10*

Output Drive Strength.

00 = Low output drive strength

01 = Medium output drive strength

10 = High output drive strength

11 = High output drive strength

Applies to all outputs except VSOUT.

**** ***0

Output Clock Invert.

0 = Noninverted pixel clock

1 = Inverted pixel clock

Applies to all clocks output on DATACK.

0x20

R/W

7:6

0*** ****

Output Select 2

Output Clock Select.

00 = Pixel clock

01 = 90° phase shifted pixel clock

10 = 2× pixel clock

11 = 0.5× pixel clock

*0** ****

Output High Impedance.

0 = Normal outputs

1 = All outputs except SOGOUT in high impedance mode

**0* ****

SOG High Impedance.

0 = Normal SOG output

1 = SOGOUT pin is in high impedance mode

***0 ****

Field Output Polarity. Sets the polarity of the field output signal.

0 = Active low => even field, active high => odd field

1 = Active low => odd field, active high => even field

**** 1***

PLL Sync Filter Enable.

0 = PLL uses raw Hsync/SOG

1 = PLL uses filtered Hsync/SOG

**** *0**

Sync Processing Input Select. Selects the sync source for the sync

processor.

0 = Sync processing uses raw Hsync/SOGIN

1 = Sync processing uses regenerated Hsync from sync filter

Must be set to 1 for proper operation.

0x21

R/W

7:0

0010 0000

Must be set to default for proper operation.

0x22

R/W

7:0

0011 0010

Must be set to default for proper operation.

AD9983A/PCB 数据表(PDF) 27 Page - Analog Devices

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