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AD9983A

Preliminary Technical Data

Rev. PrA | Page 16 of 44

AD9983A

SOGOUT

HSYNC

COAST

DATACK

SOGIN0

EXTCK/COAST

VSYNC1

MUX

VSYNC0

HSYNC1

HSYNC0

HSOUT

VSOUT/A0

SOGIN1

HSYNC

SELECT

FILTERED

HSYNC

ACTIVITY

DETECT

ACTIVITY

DETECT

ACTIVITY

DETECT

ACTIVITY

DETECT

ACTIVITY

DETECT

ACTIVITY

DETECT

POLARITY

DETECT

POLARITY

DETECT

POLARITY

DETECT

POLARITY

DETECT

SYNC SLICER

PLL CLOCK

GENERATOR

O/E FIELD

CHANNEL

SELECT

HSYNC FILTER

AND

REGENERATOR

REGENERATED

HSYNC

SET

POLARITY

SYNC

PROCESSOR

AND

VSYNC FILTER

HSYNC/VSYNC

COUNTER

REG 0x26, 0x27

SET

POLARITY

SET

POLARITY

SET

POLARITY

Figure 9. Sync Processing Block Diagram

SYNC PROCESSING

The inputs of the sync processing section of the AD9983A are

combinations of digital Hsyncs and Vsyncs, analog sync-on-

green, or sync-on-Y signals, and an optional external coast

signal. From these signals it generates a precise, jitter-free clock

from its PLL; an odd/even field signal; HSOUT and VSOUT

signals; a count of Hsyncs per Vsync; and a programmable

SOGOUT. The main sync processing blocks are the sync slicer,

sync separator, Hsync filter, Hsync regenerator, Vsync filter, and

coast generator.

• The sync slicer extracts the sync signal from the green

graphics or luminance video signal that is connected to the

SOGINx input and outputs a digital composite sync.

• The sync separator’s task is to extract Vsync from the

composite sync signal, which can come from either the sync

slicer or the HSYNCx inputs.

• The Hsync filter is used to eliminate any extraneous pulses

from the HSYNCx or SOGINx inputs, outputting a clean,

low jitter signal that is appropriate for mode detection and

clock generation.

•

The Hsync regenerator is used to recreate a clean, although

not low jitter, Hsync signal that can be used for mode

detection and counting Hsyncs per Vsync.

•

The Vsync filter is used to eliminate spurious Vsyncs,

maintain a stable timing relationship between the Vsync and

Hsync output signals, and generate the odd/even field output.

•

The coast generator creates a robust coast signal that

allows the PLL to maintain its frequency in the absence of

Hsync pulses.

Sync Slicer

The purpose of the sync slicer is to extract the sync signal from

the green graphics or luminance video signal that is connected

to the SOG input. The sync signal is extracted in a two step

process. First, the SOG input is clamped to its negative peak,

(typically 0.3 V below the black level). Next, the signal goes to a

comparator with a variable trigger level (set by Register 0x1D,

Bits[7:3]), but nominally 0.128 V above the clamped level. The

sync slicer output is a digital composite sync signal containing

both Hsync and Vsync information (see Figure 10).

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