AD9983ASLASHPCB datasheet(32/44 Pages) AD

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AD9983A

Preliminary Technical Data

Rev. PrA | Page 32 of 44

0x12—Bit[5] Hsync Input Polarity Override

This bit determines whether the chip selects the Hsync input

polarity or if it is specified. Setting this bit to 0 allows the chip

to automatically select the polarity of the input Hsync; setting it

to 1 indicates that Bit 4 of Register 0x12 specifies the polarity.

Power-up default is 0.

Table 20. Hsync Input Polarity Override Settings

Override Bit

Result

Hsync polarity determined by chip

Hsync polarity determined by user

0x12—Bit[4] Hsync Input Polarity

If Bit 5 of Register 0x12 is 1, the value of this bit specifies the

polarity of the input Hsync. Setting this bit to 0 indicates an

active low Hsync; setting this bit to 1 indicates an active high

Hsync. Power-up default is 1.

Table 21. Hsync Input Polarity Settings

Hsync Polarity Bit

Result

Hsync input polarity is negative

Hsync input polarity is positive

0x12—Bit[3] Hsync Output Polarity

This bit sets the polarity of the Hsync output. Setting this bit to

0 sets the Hsync output to active low. Setting this bit to 1 sets

the Hsync output to active high. Power-up default setting is 1.

Table 22. Hsync Output Polarity Settings

Hsync Output

Polarity Bit

Result

Hsync output polarity is negative

Hsync output polarity is positive

0x13—Bits[7:0] Hsync Duration

An 8-bit register that sets the duration of the Hsync output

pulse. The leading edge of the Hsync output is triggered by the

internally-generated, phase-adjusted PLL feedback clock. The

AD9983A then counts a number of pixel clocks equal to the

value in this register. This triggers the trailing edge of the Hsync

output, which is also phase-adjusted.

VSYNC CONTROLS

0x14—Bit[7] Vsync Source Override

This is the active Vsync override. Setting this to 0 allows the

chip to determine the active Vsync source, setting it to 1 uses

Bit 6 of Register 0x14 to determine the active Vsync source.

Power-up default value is 0.

Table 23. Active Vsync Source Override

Override

Result

Vsync source determined by chip

Vsync source determined by user

0x14—Bit[6] Vsync Source

This bit selects the source of the Vsync for sync processing only

if Bit 7 of Register 0x14 is set to 1. Setting Bit 6 to 0 specifies the

Vsync from the input pin; setting it to 1 selects Vsync from the

sync separator. Power-up default is 0.

Table 24. Active Vsync Select Settings

Select

Result

Vsync input

Vsync from sync separator

0x14—Bit[5] Vsync Input Polarity Override

This bit sets whether the chip selects the Vsync input polarity or

if it is specified. Setting this bit to 0 allows the chip to

automatically select the polarity of the input Vsync. Setting this

bit to 1 indicates that Bit 4 of Register 0x14 specifies the

polarity. Power-up default is 0.

Table 25. Vsync Input Polarity Override Settings

Override Bit

Result

Vsync polarity determined by chip

Vsync polarity determined by user

0x14—Bit[4] Vsync Input Polarity

If Bit 5 of Register 0x14 is 1, the value of this bit specifies the

polarity of the input Vsync. Setting this bit to 0 indicates an

active low Vsync; setting this bit to 1 indicates an active high

Vsync. Power-up default is 1.

Table 26. Vsync Input Polarity Settings

Override Bit

Result

Vsync input polarity is negative

Vsync input polarity is positive

0x14—Bit[3] Vsync Output Polarity

This bit sets the polarity of the Vsync output. Setting this bit to

0 sets the Vsync output to active low. Setting this bit to 1 sets

the Vsync output to active high. Power-up default is 1.

Table 27. Vsync Output Polarity Settings

Vsync Output

Polarity Bit

Result

Vsync output polarity is negative

Vsync output polarity is positive

0x14—Bit[2] Vsync Filter Enable

This bit enables the Vsync filter allowing precise placement of

the Vsync with respect to the Hsync and facilitating the correct

operation of the Hsyncs/Vsync count.

Table 28. Vsync Filter Enable

Vsync Filter Bit

Result

Vsync filter disabled

Vsync filter enabled

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