AD9983ASLASHPCB datasheet(20/44 Pages) AD

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AD9983A

Preliminary Technical Data

Rev. PrA | Page 20 of 44

DATAIN

P10

P11

HSYNCx

DATACK

8 CLOCK CYCLE DELAY

DATAOUT

2 CLOCK CYCLE DELAY

HSOUT

Figure 15. 4:4:4 Timing Mode

DATAIN

P10

P11

HSYNCx

DATACK

8 CLOCK CYCLE DELAY

CB/CROUT

CB0

CR0

CB2

CR2

YOUT

2 CLOCK CYCLE DELAY

NOTES

1. PIXEL AFTER HSOUT CORRESONDS TO BLUE INPUT.

2. EVEN NUMBER OF PIXEL DELAY BETWEEN HSOUT AND DATAOUT.

HSOUT

Figure 16. 4:2:2 Timing Mode

DATAIN

P10

P11

HSYNCx

DATACK

8 CLOCK CYCLE DELAY

2 CLOCK CYCLE DELAY

DDR NOTES

1. OUTPUT DATACK MAY BE DELAYED 1/4 CLOCK PERIOD IN THE REGISTERS.

2. SEE PROJECT DOCUMENT FOR VALUES OF F (FALLING EDGE) AND R (RISING EDGE).

3. FOR DDR 4:2:2 MODE: TIMING IS IDENTICAL, VALUES OF F AND R CHANGE.

GENERAL NOTES

1. DATA DELAY MAY VARY ± ONE CLOCK CYCLE, DEPENDING ON PHASE SETTING.

2. ADCs SAMPLE INPUT ON FALLING EDGE OF DATACK.

3. HSYNC SHOWN IS ACTIVE HIGH (EDGE SHOWN IS LEADING EDGE).

HSOUT

F0 R0 F1 R1 F2 R2 F3 R3

Figure 17. Double Data Rate (DDR) Timing Mode

HSYNC TIMING

The Hsync is processed in the AD9983A to eliminate ambiguity

in the timing of the leading edge with respect to the phase-

delayed pixel clock and data.

The Hsync input is used as a reference to generate the pixel

sampling clock. The sampling phase can be adjusted with

respect to Hsync through a full 360° in 32 steps via the phase

adjust register (to optimize the pixel sampling time). Display

systems use Hsync to align memory and display write cycles, so

it is important to have a stable timing relationship between

Hsync output (HSOUT) and the data clock (DATACK).

Three things happen to Hsync in the AD9983A. First, the

polarity of Hsync input is determined and thus has a known

output polarity. The known output polarity can be programmed

either active high or active low (Register 0x12, Bit 3). Second,

HSOUT is aligned with DATACK and data outputs. Third, the

duration of HSOUT (in pixel clocks) is set via Register 0x13.

HSOUT is the sync signal that should be used to drive the rest

of the display system.

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