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AD9983A/PCB 数据表(PDF) 18 Page - Analog Devices |
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AD9983A/PCB 数据表(HTML) 18 Page - Analog Devices |
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18 / 44 page ![]() AD9983A Preliminary Technical Data Rev. PrA | Page 18 of 44 HSYNCOUT VSYNC FILTER WINDOW EXPECTED EDGE FILTER WINDOW EQUALIZATION PULSES HSYNCIN Figure 11. Sync Processing Filter Vsync Filter and Odd/Even Fields The Vsync filter is used to eliminate spurious Vsyncs, maintain a stable timing relationship between the Vsync and Hsync output signals, and generate the odd/even field output. The filter works by examining the placement of Vsync with respect to Hsync and if necessary shifting it in time slightly. The goal is to keep the Vsync and Hsync leading edges from switching at the same time, thus eliminating confusion as to when the first line of a frame occurs. Register 0x14, Bit 2 enables the Vsync filter. Use of the Vsync filter is recommended for all cases, including interlaced video, and is required when using the Hsyncs per Vsync counter. Figure 12 and Figure 13 illustrate even/odd field determination in two situations. FIELD 1 FIELD 0 SYNC SEPARATOR THRESHOLD FIELD 1 FIELD 0 23 2 1 44 31 HSYNCIN VSYNCIN VSYNCOUT O/E FIELD ODD FIELD QUADRANT Figure 12. Vsync Filter—Odd Field FIELD 1 FIELD 0 SYNC SEPARATOR THRESHOLD FIELD 1 FIELD 0 23 2 1 44 31 HSYNCIN VSYNCIN VSYNCOUT O/E FIELD EVEN FIELD QUADRANT Figure 13. Vsync Filter—Even Field |
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