AD9983ASLASHPCB datasheet(26/44 Pages) AD

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AD9983A

Preliminary Technical Data

Rev. PrA | Page 26 of 44

Hex

Address

Read/Write,

Read Only

Bits

Default

Value

Description

***0 ****

Clamp Source Select.

0 = Use the internal clamp generated from Hsync

1 = Use the external clamp signal

**** 0***

Red Clamp Select.

0 = Clamp the red channel to ground

1 = Clamp the red channel to midscale

**** *0**

Green Clamp Select.

0 = Clamp the green channel to ground

1 = Clamp the green channel to midscale

**** **0*

Blue Clamp Select.

0 = Clamp the blue channel to ground

1 = Clamp the blue channel to midscale

**** ***0

Must be set to 0 for proper operation.

0x19

R/W

7:0

0000 1000

Clamp Placement

Places the clamp signal an integer number of clock periods after

the trailing edge of the Hsync signal.

0x1A

R/W

7:0

0010 0000

Clamp Duration

Number of clock periods that the clamp signal is actively clamping.

0x1B

R/W

0*** ****

Clamp and Offset

External Clamp Polarity Override.

0 = The chip selects the clamp polarity

1 = The polarity of the clamp signal is set by Reg. 0x1B, Bit 6

*1** ****

External Clamp Input Polarity. This bit is used only if Reg. 0x1B, Bit 7

is set to 1.

0 = Active low external clamp

1 = Active high external clamp

**0* ****

Auto-Offset Enable.

0 = Auto-offset is disabled

1 = Auto-offset is enabled (offsets become the desired clamp code)

4:3

***1 1***

Auto-Offset Update Frequency. This selects how often the auto-

offset circuit operates.

00 = every 3 clamps

01 = 48 clamps

10 = every 192 clamps

11 = every 3 Vsyncs

2:0

**** *011

Must be written to default (011) for proper operation.

0x1C

R/W

7:0

1111 1111

TestReg0

Must be set to 0xFF for proper operation.

0x1D

R/W

7:3

0111 1***

SOG Control

SOG Slicer Threshold. Sets the voltage level of the SOG slicer’s

comparator.

**** *0**

SOGOUT Polarity. Sets the polarity of the signal on the SOGOUT pin.

0 = Active low SOGOUT

1 = Active high SOGOUT

1:0

**** **00

SOGOUT Select.

00 = Raw SOG from sync slicer (SOGIN0 or SOGIN1)

01 = Raw Hsync (HSYNC0 or HSYNC1)

10 = Regenerated sync from sync filter

11 = Filtered sync from sync filter

0x1E

R/W

*** ****

Power

Channel Select Override.

0 = The chip determines which input channels to use

1 = The input channel selection is determined by Reg. 0x1E, Bit 6

*0** ****

Channel Select. Input channel select: this is used only if Reg. 0x1E,

Bit 7 is set to 1, or if syncs are present on both channels.

0 = Channel 0 syncs and data are selected

1 = Channel 1 syncs and data are selected

**1* ****

Programmable Bandwidth.

0 = Low analog input bandwidth (7 MHz)

1 = High analog input bandwidth

***1 ****

Power-Down Control Select.

0 = Manual power-down control

1 = Auto power-down control

AD9983A/PCB 数据表(PDF) 26 Page - Analog Devices

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