AD9983ASLASHPCB datasheet(34/44 Pages) AD

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AD9983A

Preliminary Technical Data

Rev. PrA | Page 34 of 44

0x19—Bits[7:0] Clamp Placement

An 8-bit register that sets the position of the internally

generated clamp. When EXTCLMP = 0 (Register 0x18, Bit 4), a

clamp signal is generated internally, at a position established by

the clamp placement register (Register 0x19) and for a duration

set by the clamp duration register (Register 0x1A). Clamping is

started a clamp placement count(Register 0x19) of pixel periods

after the trailing edge of Hsync. The clamp placement may be

programmed to any value between 1 and 255. A value of 0 is not

supported.

The clamp should be placed during a time that the input signal

presents a stable black-level reference, usually the back porch

period between Hsync and the image. When EXTCLMP = 1,

this register is ignored. Power-up default setting is 8.

0x1A—Bits[7:0] Clamp Duration

An 8-bit register that sets the duration of the internally

generated clamp. When EXTCLMP = 0 (Register 0x18, Bit 4), a

clamp signal is generated internally at a position established by

the clamp placement register (and for a duration set by the

clamp duration register). Clamping begins a clamp placement

count (Register 0x19) of pixel periods after the trailing edge of

Hsync. The clamp duration may be programmed to any value

between 1 and 255. A value of 0 is not supported.

For the best results, the clamp duration should be set to include

the majority of the black reference signal time that follows the

Hsync signal trailing edge. Insufficient clamping time can

produce brightness changes at the top of the screen, and a slow

recovery from large changes in the average picture level (APL),

or bright-ness. When EXTCLMP = 1, this register is ignored.

Power-up default setting is 20 DDR.

0x1B—Bit[7] Clamp Polarity Override

This bit is used to override the internal circuitry that

determines the polarity of the clamp signal. The power-up

default setting is 0.

Table 37. Clamp Polarity Override Settings

Override Bit

Result

Clamp polarity determined by chip

Clamp polarity determined by user

0x1B—Bit[6] Clamp Input Polarity

This bit indicates the polarity of the clamp signal only if Bit 7 of

Table 38. Clamp Polarity Override Settings

Value

Result

Active low external clamp

Active high external clamp

0x1B—Bit[5] Auto-Offset Enable

This bit selects between auto-offset mode and manual offset

mode (auto-offset disabled) (See the section on auto-offset

operation). The power-up default setting is 0.

Table 39. Auto-Offset Settings

Auto-Offset

Result

Auto-offset is disabled

Auto-offset is enabled (manual offset mode)

0x1B—Bits[4:3] Auto-Offset Update Frequency

These bits control how often the auto-offset circuit is updated

(if enabled). Updating every 64 Hsyncs is recommended. The

power-up default setting is 11.

Table 40. Auto-Offset Update Mode

Clamp Update

Result

Update offset every clamp period

Update offset every 16 clamp periods

Update offset every 64 clamp periods

Update offset every Vsync periods

0x1B—Bits[2:0]

Must be written to 011 for proper operation.

SOG CONTROL

0x1D—Bits[7:3] SOG Slicer Threshold

This register allows the comparator threshold of the SOG slicer

to be adjusted. This register adjusts it in steps of 8 mV, with the

minimum setting equaling 8 mV and the maximum setting

equaling 256 mV. The power-up default setting is 15 DDR and

corresponds to a threshold value of 128 mV.

0x1D—Bit[2] SOGOUT Polarity

This bit sets the polarity of the SOGOUT signal. The power-up

default setting is 0.

Table 41. SOGOUT Polarity Settings

SOGOUT

Result

Active low

Active high

0x1D—Bits[1:0] SOGOUT Select

These register bits control what is output on the SOGOUT pin.

Options are the raw SOG from the slicer (this is the

unprocessed SOG signal produced from the sync slicer), the

raw Hsync, the regenerated sync from the sync filter, which can

generate missing syncs either due to coasting or drop-out, or

finally the filtered sync which excludes extraneous syncs not

occurring within the sync filter window. The power-up default

setting is 0.

Table 42. SOGOUT Select

SOGOUT Select

Function

Raw SOG from sync slicer (SOGIN0 or SOGIN1)

Raw Hsync (HSYNC0 or HSYNC1)

Regenerated Hsync from sync filter

Filtered Hsync from sync filter

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