AD9983ASLASHPCB datasheet(33/44 Pages) AD

33 / 44 page

Preliminary Technical Data

AD9983A

Rev. PrA | Page 33 of 44

0x14—Bit[1] Vsync Duration Enable

This enables the Vsync duration block, which is designed to be

used with the Vsync filter. Setting the bit to 0 leaves the Vsync

output duration unchanged. Setting the bit to 1 sets the Vsync

output duration based on Register 0x15. Power-up duration is 0.

Table 29. Vsync Duration Enable

Vsync Duration Bit

Result

Vsync output duration is unchanged

Vsync output duration is set by Register

0x15

0x15—Bits[7:0] Vsync Duration

This is used to set the output duration of the Vsync, and is

designed to be used with the Vsync filter. This is valid only if

COAST AND CLAMP CONTROLS

0x16—Bits[7:0] Precoast

This register allows the internally generated coast signal to be

applied prior to the Vsync signal. This is necessary in cases

where pre-equalization pulses are present. The step size for this

control is one Hsync period. For precoast to work correctly, it is

necessary for the Vsync filter (0x14, Bit 2) and sync processing

filter (Register 0x20, Bit 1) both to be either enabled or disabled.

The power-up default is 00.

0x17—Bits[7:0] Postcoast

This register allows the internally generated Coast signal to be

applied following the Vsync signal. This is necessary in cases

where postequalization pulses are present. The step size for this

control is one Hsync period. For Postcoast to work correctly, it

is necessary for the Vsync filter (0x14, Bit 2) and sync

processing filter (0x20, Bit 1) both to be either enabled or

disabled. The power-up default is 00.

0x18—Bit[7] Coast Source

This bit is used to select the active Coast source. The choices are

the coast input pin or Vsync. If Vsync is selected, the additional

decision of using the Vsync input pin or the output from the

sync separator needs to be made (Register 0x14, Bits [7: 6]).

Table 30. Coast Source Selection Settings

Select

Result

Vsync (internal coast)

COAST input pin

0x18—Bit[6] Coast Polarity Override

This register is used to override the internal circuitry that

determines the polarity of the coast signal going into the PLL.

The power-up default setting is 0.

Table 31. Coast Polarity Override Settings

Override Bit

Result

Coast polarity determined by chip

Coast polarity determined by user

0x18—Bit[5] Coast Input Polarity

This register sets the input coast polarity when Bit 6 of

Table 32. Coast Polarity Settings

Coast Polarity Bit

Result

Coast polarity is negative

Coast polarity is positive

0x18—Bit[4] Clamp Source Select

This bit determines the source of clamp timing. A 0 enables the

clamp timing circuitry controlled by clamp placement and

clamp duration. The clamp position and duration is counted

from the leading edge of Hsync. A 1 enables the external clamp

input pin. The three channels are clamped when the clamp

signal is active. The polarity of clamp is determined by the

clamp polarity bit. The power-up default setting is 0.

Table 33. Clamp Source Selection Settings

Clamp Source

Result

Internally generated clamp

Externally provided clamp signal

0x18—Bit[3] Red Clamp Select

This bit determines whether the red channel is clamped to

ground or to midscale. The power-up default setting is 0.

Table 34. Red Clamp Select Settings

Clamp

Result

Clamp to ground

Clamp to midscale

0x18—Bit[2] Green Clamp Select

This bit determines whether the green channel is clamped to

ground or to midscale. The power-up default setting is 0.

Table 35. Green Clamp Select Settings

Clamp

Result

Clamp to ground

Clamp to midscale

0x18—Bit[1] Blue Clamp Select

This bit determines whether the blue channel is clamped to

ground or to midscale. The power-up default setting is 0.

Table 36. Blue Clamp Select Settings

Clamp

Result

Clamp to ground

Clamp to midscale

AD9983A/PCB 数据表(PDF) 33 Page - Analog Devices

AD9983A/PCB 数据表(HTML) 33 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表下载

链接网址

AD9983A/PCB 数据表(PDF) 33 Page - Analog Devices

AD9983A/PCB 数据表(HTML) 33 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表 下载

链接网址

数据表下载