Specification
NET2270 USB Interface Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 3.6, April 17, 2003
25
4.6
DMA Transactions
DMA transfers are those in which an external DMA controller transfers data between memory and one of the packet
buffers within the NET2270. DMA transfers can be configured for endpoint A or endpoint B only. The local CPU
handles transfers to/from endpoints 0 and C. The external DMA controller is programmed to perform fly-by
demand mode transfers. In this mode, transfers occur only when the NET2270 requests them and the data is
transferred between the NET2270 and local memory during the same bus transaction.
The buffer accessed from the local bus through the Endpoint Data Register or DMA port is selected as follows. As
long as DMA requests are enabled, the active buffer is selected by the DMA Endpoint Select field of the DMAREQ
register. Otherwise the active buffer is selected by the Page Select field in the PAGESEL register. The active
endpoint configuration registers are always selected by Page Select.
DMA Request Enable
Endpoint Buffer
Endpoint Registers
0
Selected by Page Select
Selected by Page Select
1
Selected by DMA Endpoint Select
Selected by Page Select
4.6.1 DMA Read
For OUT transfers (host to device), the local and host CPUs first arrange to transfer a block of data from host
memory to local memory. The local CPU programs the external DMA controller to transfer the desired number of
bytes. The signals DREQ, DACK, IOR#, and EOT are used to control the transactions between the external DMA
controller and the NET2270. DREQ and DACK are minimally needed to exchange data with the NET2270 since
the direction (read) is established by the Endpoint Direction bit in the EP_CFG register. The mode of operation is
set by the DMA Control DACK bit in the DMAREQ register. If the DMA Control DACK bit is high, then both DACK
and IOR# are needed by the NET2270 for a DMA read. If the DMA Control DACK bit is low, then only DACK is
needed.
The local CPU programs the NET2270 DMAREQ register to associate the DMA with a NET2270 endpoint (either
Endpoint A or Endpoint B). Transfers occur only when the NET2270 requests them, after the DMA Request Enable
bit is set in the DMAREQ register.
When the NET2270 has data available in an endpoint buffer, and that endpoint has been assigned to the DMA
channel, the DMA request (DREQ) signal is asserted. The external DMA controller then requests the local bus from
the local bus master. After the external DMA controller has been granted the bus, it drives a valid memory address
and asserts DACK#, IOR# (optional), and MEMW# (to memory), thus transferring a byte from an endpoint’s buffer
to local memory. The NET2270 de-asserts DREQ within T20 after the start of the transaction. If there is still data
in the buffer, the NET2270 then re-asserts DREQ within T21 after the end of the previous transaction. The DMA
transfers continue until the DMA byte count reaches zero or the EOT pin is asserted during the last DMA transfer. If
the EOT pin is asserted during the last DMA transfer, the DMA Done Interrupt bit in the IRQSTAT0 register will
be set.
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