Specification
NET2270 USB Interface Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 3.6, April 17, 2003
43
6
Interrupt and Status Register Operation
6.1
Interrupt Status Registers (IRQSTAT0, IRQSTAT1)
Bits 3:0 of the IRQSTAT0 register indicate whether one of the endpoints 0, A-C has an interrupt pending. These
bits cannot be written, and can cause a local interrupt if the corresponding interrupt enable bits are set in the
IRQENB0 register. Bit 7 is automatically set when a start-of-frame (SOF) token is received, and is cleared by
writing a 1. This bit can cause a local interrupt if the corresponding interrupt enable bit is set in the IRQENB0
register. Note that the interrupt bits can be set without the corresponding interrupt enable bit being set. This allows
the local CPU to operate in a polled, as well as an interrupt driven environment.
Bits 6:5 of IRQSTAT0 and bits 7:4 and 2:1 of IRQSTAT1 are set when a particular event occurs in the NET2270,
and are cleared by writing a 1 to the corresponding bit. These bits can cause a local interrupt if the corresponding
interrupt enable bits are set in the IRQENB0 and IRQENB1 registers.
Bit 3 of IRQSTAT1 is set when there is a suspend request from the host, but it typically not enabled to generate an
interrupt. Writing a 1 clears this bit and causes the 2270 to enter the suspend state.
6.2
Endpoint Response Registers (EPRSP_CLR, EPRSP_SET)
Each endpoint has a pair of Endpoint Response Registers. The bits in these registers determine how the NET2270
will respond to various situations during a USB transaction. Writing a 1 to any of the bits in the EP_RSPCLR
register will clear the corresponding bits. Writing a 1 to any of the bits in the EP_RSPSET register will set the
corresponding bits. Reading either of the registers returns the current state of the bits.
6.3
Endpoint Status Register (EP_STAT0, EP_STAT1)
Each endpoint has a pair of Endpoint Status Registers. Each of the bits of these registers is set when a particular
endpoint event occurs, and is cleared by writing a 1 to the corresponding bit. A local interrupt can be generated if
the corresponding interrupt enable bits are set in the EP_IRQENB registers. Reading the EP_STAT registers
returns the current state of the bits.
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