
Specification
NET2270 USB Interface Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 3.6, April 17, 2003
34
Packet Validated
Amount of Data in buffer
Action
0
< Max Packet Size
NAK to host
X
>= Max Packet Size
Return data to host
1
empty
Zero length packet to host
1
>0
Return data to host
After each packet has been sent to the host, the Data Packet Transmitted Interrupt bit is set.
If a packet is not successfully transmitted (Timeout status bit set), the Data Packet Transmitted Interrupt bit will not
be set, and the same packet is sent to the host when another IN token is received. The retry operation is transparent
to the local CPU.
If the host tries to read more data than was requested in the setup packet, the local CPU should set the STALL bit
for the endpoint.
After all of the optional Data transaction packets have been transmitted, the host will send an OUT token, followed
by a zero length data packet, signifying the Status transaction. The Control Status Interrupt bit is set after the OUT
token of the Status transaction has been received. Until the Control Status Phase Handshake bit is cleared by the
local CPU, the NET2270 will respond to the Status transaction with NAKs, indicating that the device is still
processing the command specified by the Setup transaction. When the Control Status Phase Handshake bit has been
cleared by the local CPU, the NET2270 will respond with an ACK (transfer OK) or STALL (Endpoint 0 is stalled).
5.6.3 Isochronous Endpoints
Isochronous endpoints are used for the transfer of time critical data. Isochronous transfers do not support any
handshaking or error checking protocol, and are guaranteed a certain amount of bandwidth during each frame. The
Serial Interface Engine in the NET2270 ignores CRC and bit stuffing errors during isochronous transfers, but sets
the handshaking status bits in the EP_STAT registers the same as for non-isochronous packets so that the local
CPU can detect errors. Isochronous endpoints are unidirectional, with the direction defined by the endpoint
configuration registers.
For isochronous endpoints, the packet buffer size must be equal to or greater than the maximum packet size. The
maximum packet size for an isochronous endpoint ranges from 1 to 1024 bytes.
For an Isochronous OUT endpoint, the local CPU or DMA can read data from the endpoint buffer after an entire
packet has been received. If the endpoint buffer is the same size as the maximum packet size, then the ISO
bandwidth must be set such that the buffer can be emptied before the next ISO packet arrives.
For an Isochronous IN endpoint, the local CPU or DMA can write data to one endpoint buffer at the same time that
data is being transmitted to the USB from the other endpoint buffer (double-buffered mode only).