Specification
NET2270 USB Interface Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 3.6, April 17, 2003
56
8.5.5 (Address 30h; OURADDR) Our Current USB Address
Bits
Description
Read
Write
Default
Value
7
Force Immediate. If this bit is set when this register is being written, the NET2270
USB address is updated immediately, without waiting for a valid status phase from
the USB host.
0
Yes/Force
0
6:0
Our Address. This field contains the current USB address of the device. This field
is cleared when a root port reset is detected. After this field is written, the register
isn’t actually updated until the corresponding status phase of the control write
transfer completes successfully. This feature allows the firmware to write this field
as soon as the Setup packet is received, rather than waiting for a successful status
phase. Refer to sections 9.2.6.3 and 9.4.6 of the USB 2.0 specification.
Yes
Yes
0
8.5.6 (Address 31h; USBDIAG) USB Diagnostic Register
Bits
Description
Read
Write
Default
Value
7:6
Reserved
Yes
No
0
5
Force Bi-Directional to Inputs. When this bit is set, all bi-directional pins on the
chip are forced to inputs in test mode.
Yes
Yes
1
4
Fast Times. When this bit is set, the frame counter operates at a fast speed for
factory chip testing purposes only.
Yes
Yes
0
3
Reserved.
Yes
No
0
2
Force Receive Error. When this bit is set, an error is forced on the next received
data packet. As a result, the packet will not be acknowledged. This bit is
automatically cleared at the end of the next packet.
Yes
Yes/Set
0
1
Prevent Transmit Bit-Stuff. When this bit is set, normal bit-stuffing is suppressed
during the next transmitted data packet. This will cause a bit-stuffing error when six
or more consecutive bits of ‘1’ are in the data stream. This bit is automatically
cleared at the end of the next packet.
Yes
Yes/Set
0
0
Force Transmit CRC Error. When this bit is set, a CRC error is forced on the next
transmitted data packet. Inverting the most significant bit of the calculated CRC
generates the CRC error. This bit is automatically cleared at the end of the next
packet.
Yes
Yes/Set
0
8.5.7 (Address 32h; USBTEST) USB Test Modes
Bits
Description
Read
Write
Default
Value
7:3
Reserved.
Yes
No
0
2:0
Test Mode Select. See sections 7.1.20 and 9.4.9 of the USB 2.0 specification.
Value
Test
000
Normal Operation
001
Test_J
010
Test_K
011
Test_SE0_NAK
100
Test_Packet
101
Test_Force_Enable
110
Reserved
111
Reserved
Yes
Yes
0
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