Specification
NET2270 USB Interface Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 3.6, April 17, 2003
50
47h
Indirect Only
SETUP7
Setup byte 7
8.4
Main Control Registers
8.4.1 (Address 00h; REGADDRPTR) Indirect Register Address Pointer
Bits
Description
Read
Write
Default
Value
7
Reserved.
0
No
0
6:0
Register Address. Register Address Pointer used for indirect register addressing.
Yes
Yes
0
8.4.2 (Address 01h; REGDATA) Indirect Register Data
Bits
Description
Read
Write
Default
Value
15:0
Register Data. Register Data port for indirect register addressing. For 8-bit bus
widths, data is transferred on bits [7:0].
For 16-bit buffer accesses, data is
transferred on bits [15:0].
Yes
Yes
0
8.4.3 (Address 02h; IRQSTAT0) Interrupt Status Register (low byte)
Bits
Description
Read
Write
Default
Value
7
SOF Interrupt. This bit indicates when a start-of-frame packet has been received by
the NET2270. Writing a 1 clears this status bit.
Yes
Yes/CLR
0
6
DMA Done Interrupt. This bit indicates that the EOT# input has been asserted or
the EP_TRANSFER counter reaches zero during a DMA transfer to an IN endpoint.
Writing a 1 clears this status bit. This bit is set independently of the corresponding
interrupt enable bit.
Yes
Yes/CLR
0
5
Setup Packet Interrupt. This bit is set when a setup packet has been received from
the host. Writing a 1 clears this status bit.
Yes
Yes/CLR
0
4
Reserved.
0
No
0
3
Endpoint C Interrupt. This bit conveys the interrupt status for Endpoint C. When
set, Endpoint C’s interrupt status register should be read to determine the cause of
the interrupt. This bit is set independently of the interrupt enable bit.
Yes
No
0
2
Endpoint B Interrupt. This bit conveys the interrupt status for Endpoint B. When
set, Endpoint B’s interrupt status register should be read to determine the cause of
the interrupt. This bit is set independently of the interrupt enable bit.
Yes
No
0
1
Endpoint A Interrupt. This bit conveys the interrupt status for Endpoint A. When
set, Endpoint A’s interrupt status register should be read to determine the cause of
the interrupt. This bit is set independently of the interrupt enable bit.
Yes
No
0
0
Endpoint 0 Interrupt. This bit conveys the interrupt status for Endpoint 0. When
set, Endpoint 0’s interrupt status register should be read to determine the cause of the
interrupt. This bit is set independently of the interrupt enable bit.
Yes
No
0
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