Specification
NET2270 USB Interface Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 3.6, April 17, 2003
7
1
Introduction
1.1
Features
•
USB Specification Version 2.0 Compliant (high and full speed)
•
Interfaces between a local CPU bus and a USB bus
•
Supports USB Full Speed (12 Mb/sec) and High Speed (480 Mb/sec)
•
Supports optional Split Bus DMA, with dedicated DMA and CPU access
•
Provides 3 Configurable Endpoints, in addition to Endpoint 0
•
Each endpoint can be Isochronous, Bulk, or Interrupt, as well as IN or OUT
•
Supports Max Packet Size up to 1K bytes, double buffered
•
Internal 2 Kbyte memory provides transmit and receive buffers
•
Local CPU bus easily interfaces to generic CPUs
•
8-bit or 16-bit CPU or DMA bus transfers
•
Multiple register address modes supports both direct and indirect register addressing
•
Automatic retry of failed packets
•
Diagnostic register allows forced USB errors
•
Software controlled disconnect allows re-enumeration
•
Atomic operation to set and clear status bits, simplifying software
•
Low power CMOS in 64 Pin Plastic TQFP Package
•
30 MHz oscillator with internal phase-lock loop multiplier
•
Provides an output clock to the local bus - 8 programmable frequencies from OFF to 60 MHz
•
3.3V operating voltage with 5V tolerant I/O
1.2
Overview
The NET2270 USB Interface Controller allows control, isochronous, bulk and interrupt transfers between
a local bus and a Universal Serial Bus (USB). The NET2270 supports the Device side of a connection
between a USB host computer and intelligent peripherals such as image scanners, printers, and digital
cameras.
The six main modules of the NET2270 are the USB Transceiver, Serial Interface Engine, USB Protocol
Controller, Endpoint Packet Buffers, Local Bus Interface, and the Configuration Registers.
USB Transceiver:
•
Supports Full Speed (12 MHz) or High Speed (480 MHz) operation.
•
Serial data transmitter and receiver.
•
Parallel data interface to SIE.
•
Single parallel data clock output with on-chip PLL to generate higher speed serial data clocks
•
Data and clock recovery from USB serial data stream.
•
SYNC/EOP generation and checking.
•
Bit-stuffing/unstuffing; bit stuff error detection
•
Logic to facilitate Resume signaling
•
Logic to facilitate Wake Up and Suspend detection
•
Ability to switch between Full-Speed and High-Speed terminations/signaling
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
