Specification
NET2270 USB Interface Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 3.6, April 17, 2003
26
D0
NetChip Technology; NET2270; DMA Read; 12/10/02; DMARD.TD
D1
0ns
50ns
100ns
150ns
DREQ
DACK#
IOR# (Optional)
LD[15:0]
EOT# (Optional)
4.6.2 DMA Write
For IN transfers (device to host), the local and host CPUs first arrange to transfer a block of data from local memory
to host memory. The local CPU programs the external DMA controller to transfer the desired number of bytes. The
NET2270 EP_TRANSFER register is also programmed with the desired transfer size (in bytes). The transfer size
programmed into the EP_TRANSFER register can span many packets, allowing a single DMA setup to transfer
multiple packets. The DMA Request signal (DREQ) is asserted anytime there is space available in the buffer. The
endpoint’s Max Packet Size register controls the maximum number of bytes transmitted to the host in a single
packet. A short packet will be sent if there are remaining bytes to be sent when all EP_TRANSFER bytes have
been written or when EOT has been asserted during the last DMA cycle.
The signals DREQ, DACK, IOW#, and EOT are used to control the transactions between the external DMA
controller and the NET2270. DREQ and DACK are minimally needed to exchange data with the NET2270 since
the direction (write) is established by the Endpoint Direction bit in the EP_CFG register. The mode of operation is
set by the DMA Control DACK bit in the DMAREQ register. If the DMA Control DACK bit is high, then both DACK and
IOW# are needed by the NET2270 for a DMA write. If the DMA Control DACK bit is low, then only DACK is
needed.
The local CPU programs the NET2270 DMAREQ register to associate the DMA with a NET2270 endpoint (either
Endpoint A or Endpoint B). Transfers occur only when the NET2270 requests them, after the DMA Request Enable
bit is set in the DMAREQ register.
As long as there is space available in the selected endpoint’s buffer, and there are still bytes to be transferred, the
NET2270 will request DMA transfers by asserting DREQ. The external DMA controller then requests the local bus
from the local CPU. After the DMA controller has been granted the bus, it drives DACK#, IOW# (optional), and
MEMR# (to memory) to transfer a byte from memory to the endpoint’s buffer. The NET2270 de-asserts DREQ
within T20 after the start of the transaction. If there is still space in the buffer and there are more bytes to be
transferred, the NET2270 re-asserts DREQ within T21 after it was de-asserted.
The USB host sends an IN token to the NET2270 and starts an IN data transaction from the selected endpoint’s
buffer. The DMA transfers continue until EP_TRANSFER bytes have been transferred or EOT has been asserted.
If the EOT pin is asserted (during the last DMA transfer) or the EP_TRANSFER counter reaches zero, the DMA
Done Interrupt bit in the IRQSTAT0 register will be set.
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
