AT83C5136-RDTUL datasheet(127/171 Pages) ATMEL

127 / 171 page

127

AT83C5134/35/36

7683B–USB–03/07

Reset Value = 00h

Table 90. UEPSTAX (S:CEh) USB Endpoint X Status Register

DIR

RXOUTB1

STALLRQ

TXRDY

STL/CRC

RXSETUP

RXOUTB0

TXCMP

Bit Number

Bit

Mnemonic

Description

DIR

Control Endpoint Direction

This bit is used only if the endpoint is configured in the control type (seeSection “UEPCONX Register UEPCONX (S:D4h)

USB Endpoint X Control Register”).

This bit determines the Control data and status direction.

The device firmware will set this bit ONLY for the IN data stage, before any other USB operation. Otherwise, the device

firmware will clear this bit.

RXOUTB1

Received OUT Data Bank 1 for Endpoints 4, 5 and 6 (Ping-pong mode)

This bit is set by hardware after a new packet has been stored in the endpoint FIFO data bank 1 (only in Ping-pong mode).

Then, the endpoint interrupt is triggered if enabled (see“UEPINT Register UEPINT (S:F8h read-only) USB Endpoint

Interrupt Register” on page 131) and all the following OUT packets to the endpoint bank 1 are rejected (NAK’ed) until this

bit has been cleared, excepted for Isochronous Endpoints.

This bit will be cleared by the device firmware after reading the OUT data from the endpoint FIFO.

STALLRQ

Stall Handshake Request

Set this bit to request a STALL answer to the host for the next handshake.Clear this bit otherwise.

For CONTROL endpoints: cleared by hardware when a valid SETUP PID is received.

TXRDY

TX Packet Ready

Set this bit after a packet has been written into the endpoint FIFO for IN data transfers. Data will be written into the

endpoint FIFO only after this bit has been cleared. Set this bit without writing data to the endpoint FIFO to send a Zero

Length Packet.

This bit is cleared by hardware, as soon as the packet has been sent for Isochronous endpoints, or after the host has

acknowledged the packet for Control, Bulk and Interrupt endpoints. When this bit is cleared, the endpoint interrupt is

triggered if enabled (see“UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register” on page 131).

STLCRC

Stall Sent/CRC error flag

- For Control, Bulk and Interrupt Endpoints:

This bit is set by hardware after a STALL handshake has been sent as requested by STALLRQ. Then, the endpoint

interrupt is triggered if enabled (see“UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register” on

page 131)

It will be cleared by the device firmware.

- For Isochronous Endpoints (Read-Only):

This bit is set by hardware if the last received data is corrupted (CRC error on data).

This bit is updated by hardware when a new data is received.

RXSETUP

Received SETUP

This bit is set by hardware when a valid SETUP packet has been received from the host. Then, all the other bits of the

read-only) USB Endpoint Interrupt Register” on page 131).

It will be cleared by the device firmware after reading the SETUP data from the endpoint FIFO.

RXOUTB0

Received OUT Data Bank 0 (see also RXOUTB1 bit for Ping-pong Endpoints)

This bit is set by hardware after a new packet has been stored in the endpoint FIFO data bank 0. Then, the endpoint

interrupt is triggered if enabled (see“UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register” on

page 131) and all the following OUT packets to the endpoint bank 0 are rejected (NAK’ed) until this bit has been cleared,

excepted for Isochronous Endpoints. However, for control endpoints, an early SETUP transaction may overwrite the

content of the endpoint FIFO, even if its Data packet is received while this bit is set.

This bit will be cleared by the device firmware after reading the OUT data from the endpoint FIFO.

TXCMPL

Transmitted IN Data Complete

This bit is set by hardware after an IN packet has been transmitted for Isochronous endpoints and after it has been

accepted (ACK’ed) by the host for Control, Bulk and Interrupt endpoints. Then, the endpoint interrupt is triggered if

enabled (see“UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register” on page 131).

This bit will be cleared by the device firmware before setting TXRDY.

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