ST92F124 datasheet(136/429 Pages) STMICROELECTRONICS

部件名	ST92F124

功能描述	8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TM(EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

PDF	429 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)

CLOCK CONTROL REGISTERS (Cont’d)

PLL CONFIGURATION REGISTER (PLLCONF)

R246 - Read/Write

Reset Value: 0x00 x111

Bit 7 = FREEN: PLL Free Running Mode Enable

0: PLL Free Running Mode disabled

1: PLL Free Running Mode enabled

When this bit is set, even if the DX[2:0] bits are all

set to 1, the PLL is not stopped but provides a slow

frequency back-up clock, selectable by the

CSU_CKSEL bit of the CLK_FLAG register (with-

out needing to have the LOCK bit equal to ‘1’).

Bits 5:4 = MX[1:0]: PLL Multiplication Factor.

Refer to Table 29 for multiplier settings.

WARNING: After these bits are modified, take

care that the PLL lock-in time has elapsed before

setting the CSU_CKSEL bit in the CLK_FLAG reg-

ister.

Bits 2:0 = DX[2:0]: PLL output clock divider factor.

Refer to Table 30 for divider settings.

FREEN

MX1

MX0

DX2

DX1

DX0

Table 29. PLL Multiplication Factors

MX1

MX0

CLOCK2 x

Table 30. PLL Divider Factors

DX2

DX1

DX0

000

PLL CLOCK/1

001

PLL CLOCK/2

010

PLL CLOCK/3

011

PLL CLOCK/4

100

PLL CLOCK/5

101

PLL CLOCK/6

110

PLL CLOCK/7

111

CLOCK2

(PLL OFF, Reset State)

ST92F124 数据表(PDF) 136 Page - STMicroelectronics

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