ST92F124 datasheet(135/429 Pages) STMICROELECTRONICS

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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)

CLOCK CONTROL REGISTERS (Cont’d)

CLOCK FLAG REGISTER (CLK_FLAG)

R242 -Read/Write

Reset Value: 0110 1000 after a Flash LVD Reset

Reset Value: 0100 1000 after a Watchdog Reset

Reset Value: 0010 1000 after a Software Reset

Reset Value: 0000 1000 after an External Reset

WARNING: If you select the CK_AF as system

clock and turn off the oscillator (bits R240.2 and

R242.4 at 1), in order to switch back to the crystal

clock by resetting the R240.2 bit, you must first

wait for the oscillator to restart correctly.

Bit 7 = EX_STP: External Stop flag.

This bit is set by hardware/software and cleared by

software.

0: No External Stop condition occurred

1: External Stop condition occurred

Note: This bit is set after the end of the instruction

being executed when the microcontroller enters

stop mode. So, if this instruction is a reading of the

CLK_FLAG register, this bit will still be read as 0.

Next reading will give 1 as result.

Bit 6 = WDGRES: Watchdog reset flag.

This bit is read only.

0: No Watchdog reset occurred

1: Watchdog reset occurred

Bit 5 = SOFTRES: Software Reset Flag.

This bit is read only.

0: No software reset occurred

1: Software reset occurred (HALT instruction)

If both SOFTRES and WDGRES are set to 1, the

last reset event generator was a Flash LVD reset.

Table 28. Reset Flags

Bit 4 = XTSTOP: External Stop Enable.

0: External stop disabled

1: The Xtal oscillator will be stopped as soon as

the CK_AF clock is present and selected,

whether this is done explicitly by the user pro-

gram, or as a result of WFI, if WFI_CKSEL has

previously been set to select the CK_AF clock

during WFI.

Note: When the program writes ‘1’ to the XTSTOP

bit, it will still be read as 0 as long as the CKAF_ST

bit is reset (CKAF_ST=0). In this case, take care of

this behaviour, because a subsequent AND with

‘1’ or a OR with ‘0’ to the XSTOP bit before setting

the CKAF_ST bit will prevent the oscillator from

being stopped.

Bit 3 = XT_DIV16: CLOCK/16 Selection.

This bit is set and cleared by software. An interrupt

is generated when the bit is toggled.

0: CLOCK2/16 is selected and the PLL is off

1: The input is CLOCK2 (or the PLL output de-

pending on the value of CSU_CKSEL)

Bit 2 = CKAF_ST: (Read Only)

If set, indicates that the alternate function clock

has been selected. If no clock signal is present on

the CK_AF pin, the selection will not occur. If re-

set, the PLL clock, CLOCK2 or CLOCK2/16 is se-

lected (depending on bit 0).

Bit 1= LOCK: PLL locked-in

This bit is read only.

0: The PLL is turned off or not locked and cannot

be selected as system clock source.

1: The PLL is locked

Bit 0 = CSU_CKSEL: CSU Clock Select.

This bit is set and cleared by software. It is also

cleared by hardware when:

– bits DX[2:0] (PLLCONF) are set to 111;

– the quartz is stopped (by hardware or software);

– WFI is executed while the LPOWFI bit is set;

– the XT_DIV16 bit (CLK_FLAG) is forced to ’0’;

– STOP mode is entered.

This prevents the PLL, when not yet locked, from

providing an irregular clock. Furthermore, a ‘0’

stored in this bit speeds up the PLL’s locking.

0: CLOCK2 provides the system clock

1: The PLL Multiplier provides the system clock if

the LOCK bit is set to 1

If the FREEN bit is set, this bit selects this clock in-

dependently by the LOCK bit.

NOTE: Setting the CKAF_SEL bit overrides any

other clock selection. Resetting the XT_DIV16 bit

overrides the CSU_CKSEL selection (see Figure

61).

EX_

STP

WDG

RES

SOFT

RES

XT-

STOP

XT_

DIV16

CKAF_

CSU_

CK-

SEL

WDGRES

SOFTRES

External Reset

Software Reset

Watchdog Reset

LVD Reset

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