ST92F124 datasheet(131/429 Pages) STMICROELECTRONICS

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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)

CLOCK MANAGEMENT (Cont’d)

7.3.6 Interrupt Generation

System clock selection modifies the CLKCTL and

CLK_FLAG registers.

The clock control unit generates an external inter-

rupt request (INTD0) in the following conditions:

– when CK_AF and CLOCK2/16 are selected or

deselected as system clock source,

– when the system clock restarts after a hardware

stop (when the STOP MODE feature is availa-

ble on the specific device).

– when the PLL loses the programmed frequency

in which it was locked, and when it re-locks

This interrupt can be masked by resetting the

INT_SEL bit in the CLKCTL register. Note that this

is the only case in the ST9 where an interrupt is

generated with a high to low transition.

Table 27. Summary of Operating Modes using main Crystal Controlled Oscillator

MODE

INTCLK

CPUCLK DIV2 PRS0-2

CSU_CKSEL MX0-1 DX2-0 LPOWFI

WFI_CK

SEL

XT_DIV16

PLL x BY 14

XTAL/2

x (14/D)

INTCLK/

N-1

1 0

D-1

PLL x BY 10

XTAL/2

x (10/D)

INTCLK/

N-1

0 0

D-1

PLL x BY 8

XTAL/2

x (8/D)

INTCLK/

N-1

1 1

D-1

PLL x BY 6

XTAL/2

x (6/D)

INTCLK/

N-1

0 1

D-1

SLOW 1

XTAL/2

INTCLK/

N-1

111

SLOW 2

XTAL/32

INTCLK/

1N-1

SLOW3

CK_AF

CK_AF/N

N-1

WFI

If LPOWFI=0, no changes occur on INTCLK, but CPUCLK is stopped anyway.

LOW POW-

ER WFI 1

XTAL/32

STOP

LOW POW-

ER WFI 2

CK_AF

STOP

RESET

XTAL/2

INTCLK

111

EXAMPLE

XTAL=4.4

MHz

2.2*10/2

= 11MHz

11MHz

001

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