ST92F124 datasheet(129/429 Pages) STMICROELECTRONICS

129 / 429 page

129/429

ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)

CLOCK MANAGEMENT (Cont’d)

7.3.1 PLL Clock Multiplier Programming

The CLOCK1 signal generated by the oscillator

drives a programmable divide-by-two circuit. If the

DIV2 control bit in MODER is set (Reset Condi-

tion), CLOCK2, is equal to CLOCK1 divided by

two; if DIV2 is reset, CLOCK2 is identical to

CLOCK1. Since the input clock to the Clock Multi-

plier circuit requires a 50% duty cycle for correct

PLL operation, the divide by two circuit should be

enabled when a crystal oscillator is used, or when

the external clock generator does not provide a

50% duty cycle. In practice, the divide-by-two is

virtually always used in order to ensure a 50% duty

cycle signal to the PLL multiplier circuit.

When the PLL is active, it multiplies CLOCK2 by 6,

8, 10 or 14, depending on the status of the MX[0:1]

bits in PLLCONF. The multiplied clock is then di-

vided by a factor in the range 1 to 7, determined by

the status of the DX[0:2] bits; when these bits are

programmed to 111, the PLL is switched off.

Following a RESET phase, programming bits

DX0-2 to a value different from 111 will turn the

PLL on. After allowing a stabilization period for the

PLL,

setting

the

CSU_CKSEL

bit

the

CLK_FLAG Register selects the multiplier clock.

The RCCU contains a frequency comparator be-

tween CLOCK2 and the PLL clock output that ver-

ifies if the PLL reaches the programmed frequency

and has stabilized (locked status). When this con-

dition occurs, the LOCK bit in the CLK_FLAG reg-

ister is set to 1 by hardware and this value is main-

tained as long as the PLL is locked. The LOCK bit

is set back to 0 if for some reason (change of MX

bit value, stop and restart of PLL or CLOCK2,

etc.), the PLL loses the programmed frequency in

which it was locked.

The PLL selection as system clock is further con-

ditioned by the status of the Voltage Regulator:

when it is not providing a stabilized supply voltage,

the PLL cannot be selected.

The maximum frequency allowed for INTCLK is

24 MHz. Care is required, when programming the

PLL multiplier and divider factors, not to exceed

the maximum permissible operating frequency for

INTCLK, according to supply voltage, as reported

in Electrical Characteristics section.

The ST9 being a static machine, there is no lower

limit for INTCLK. However, some peripherals have

their own minimum internal clock frequency limit

below which the functionality is not guaranteed.

7.3.2 PLL Free Running Mode

The PLL is able to provide a 50-kHz clock, usable

slow

program

execution.

This

mode

controlled by the FREEN and DX[2:0] bits in the

PLLCONF register: when the PLL is off and the

FREEN bit is set to 1 (i.e. when the FREEN and

DX[2:0] bits are set to 1), the PLL provides this

clock. The selection of this clock is also managed

by the CSU_CKSEL bit but is not conditioned by

the LOCK bit. To avoid unpredictable behaviour of

the PLL clock, Free Running mode must be set

and reset by the user only when the PLL clock is

not the system clock, i.e. when the CSU_CKSEL

bit is reset.

In addition, when the PLL provides the internal

clock, if the clock signal disappears (for instance

due to a broken or disconnected resonator...), a

safety clock signal is automatically provided, al-

lowing the ST9 to perform some rescue opera-

tions.

Typ. Safety clock frequency = 800 kHz / Div,

where Div depends on the DX[0..2] bits of the PLL-

CONF register (R246, page55).

Table 26. Free Running Clock Frequency

DX2

DX1

DX0

DIV

CK (Typ.)

400 kHz

200 kHz

133 kHz

100 kHz

80 kHz

67 kHz

57 kHz

111

50 kHz

(CSU_CKSEL=0;

FREEN=1)

111

CLOCK2

(CSU_CKSEL=0;

FREEN=0)

ST92F124 数据表(PDF) 129 Page - STMicroelectronics

ST92F124 数据表(HTML) 129 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载