ST92F124 datasheet(125/429 Pages) STMICROELECTRONICS

125 / 429 page

125/429

ST92F124/F150/F250 - ON-CHIP DIRECT MEMORY ACCESS (DMA)

6.6 DMA REGISTERS

As each peripheral DMA channel has its own spe-

cific control registers, the following register list

should be considered as a general example. The

names and register bit allocations shown here

may be different from those found in the peripheral

chapters.

DMA COUNTER POINTER REGISTER (DCPR)

Read/Write

Address set by Peripheral

Reset value: undefined

Bit 7:1 = C[7:1]: DMA Transaction Counter Point-

er.

Software should write the pointer to the DMA

Transaction Counter in these bits.

Bit 0 = RM: Register File/Memory Selector.

This bit is set and cleared by software.

0: DMA transactions are with memory (see also

DAPR.DP)

1: DMA transactions are with the Register File

GENERIC EXTERNAL PERIPHERAL INTER-

RUPT AND DMA CONTROL (IDCR)

Read/Write

Address set by Peripheral

Reset value: undefined

Bit 5 = IP: Interrupt Pending.

This bit is set by hardware when the Trigger Event

occurs. It is cleared by hardware when the request

is acknowledged. It can be set/cleared by software

in order to generate/cancel a pending request.

0: No interrupt pending

1: Interrupt pending

Bit 4 = DM: DMA Request Mask.

This bit is set and cleared by software. It is also

cleared when the transaction counter reaches

zero (unless SWAP mode is active).

0: No DMA request is generated when IP is set.

1: DMA request is generated when IP is set

Bit 3 = IM: End of block Interrupt Mask.

This bit is set and cleared by software.

0: No End of block interrupt request is generated

when IP is set

1: End of Block interrupt is generated when IP is

set. DMA requests depend on the DM bit value

as shown in the table below.

Bit 2:0 = PRL[2:0]: Source Priority Level.

These bits are set and cleared by software. Refer

to Section 6.2 DMA PRIORITY LEVELS for a de-

scription of priority levels.

DMA ADDRESS POINTER REGISTER (DAPR)

Read/Write

Address set by Peripheral

Reset value: undefined

Bit 7:1 = A[7:1]: DMA Address Register(s) Pointer

Software should write the pointer to the DMA Ad-

dress Register(s) in these bits.

Bit 0 = PS: Memory Segment Pointer Selector:

This bit is set and cleared by software. It is only

meaningful if DCPR.RM=0.

0: The ISR register is used to extend the address

of data transferred by DMA (see MMU chapter).

1: The DMASR register is used to extend the ad-

dress of data transferred by DMA (see MMU

chapter).

PRL2 PRL1 PRL0

DM IM Meaning

A DMA request generated without End of Block

interrupt when IP=1

A DMA request generated with End of Block in-

terrupt when IP=1

No End of block interrupt or DMA request is

generated when IP=1

An End of block Interrupt is generated without

associated DMA request (not used)

PRL2 PRL1 PRL0 Source Priority Level

0 Highest

001

010

011

100

101

110

7 Lowest

ST92F124 数据表(PDF) 125 Page - STMicroelectronics

ST92F124 数据表(HTML) 125 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ST92F124 数据表(PDF) 125 Page - STMicroelectronics

ST92F124 数据表(HTML) 125 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载