ST92F124 datasheet(190/429 Pages) STMICROELECTRONICS

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MULTIFUNCTION TIMER (MFT)

MULTIFUNCTION TIMER (Cont’d)

10.4.2 Functional Description

The MFT operating modes are selected by pro-

gramming the Timer Control Register (TCR) and

the Timer Mode Register (TMR).

10.4.2.1 Trigger Events

A trigger event may be generated by software (by

setting either the CP0 or the CP1 bits in the

T_FLAGR register) or by an external source which

may be programmed to respond to the rising edge,

the falling edge or both by programming bits A0-

A1 and B0-B1 in the T_ICR register. This trigger

event can be used to perform a capture or a load,

depending on the Timer mode (configured using

the bits in Table 41).

An event on the TxINA input or setting the CP0 bit

triggers a capture to, or a load from the REG0R

10.4.2.11).

An event on the TxINB input or setting the CP1 bit

triggers a capture to, or a load from the REG1R

In addition, in the special case of "Load from

REG0R and monitor on REG1R", it is possible to

use the TxINB input as a trigger for REG0R."

10.4.2.2 One Shot Mode

When the counter generates an overflow (in up-

count mode), or an underflow (in down-count

mode), that is to say when an End Of Count condi-

tion is reached, the counter stops and no counter

reload occurs. The counter may only be restarted

by an external trigger on TxINA or B or a by soft-

ware trigger on CP0 only. One Shot Mode is en-

tered by setting the CO bit in TMR.

10.4.2.3 Continuous Mode

Whenever the counter reaches an End Of Count

condition, the counting sequence is automatically

restarted and the counter is reloaded from REG0R

(or from REG1R, when selected in Biload Mode).

Continuous Mode is entered by resetting the C0 bit

in TMR.

10.4.2.4 Triggered And Retriggered Modes

A triggered event may be generated by software

(by setting either the CP0 or the CP1 bit in the

T_FLAGR register), or by an external source

which may be programmed to respond to the rising

edge, the falling edge or both, by programming

bits A0-A1 and B0-B1 in T_ICR.

In One Shot and Triggered Mode, every trigger

event arriving before an End Of Count, is masked.

In One Shot and Retriggered Mode, every trigger

received while the counter is running, automatical-

ly reloads the counter from REG0R. Triggered/Re-

triggered Mode is set by the REN bit in TMR.

The TxINA input refers to REG0R and the TxINB

input refers to REG1R.

WARNING. If the Triggered Mode is selected

when the counter is in Continuous Mode, every

trigger is disabled, it is not therefore possible to

synchronise the counting cycle by hardware or

software.

10.4.2.5 Gated Mode

In this mode, counting takes place only when the

external gate input is at a logic low level. The se-

lection of TxINA or TxINB as the gate input is

made by programming the IN0-IN3 bits in T_ICR.

10.4.2.6 Capture Mode

The REG0R and REG1R registers may be inde-

pendently set in Capture Mode by setting RM0 or

RM1 in TMR, so that a capture of the current count

value can be performed either on REG0R or on

REG1R, initiated by software (by setting CP0 or

CP1 in the T_FLAGR register) or by an event on

the external input pins.

WARNING. Care should be taken when two soft-

ware captures are to be performed on the same

be present between the first CP0/CP1 bit set and

the subsequent CP0/CP1 bit reset instructions.

10.4.2.7 Up/Down Mode

The counter can count up or down depending on

the state of the UDC bit (Up/Down Count) in TCR,

or on the configuration of the external input pins,

which have priority over UDC (see Input pin as-

signment in T_ICR). The UDCS bit returns the

counter up/down current status (see also the Up/

Down Autodiscrimination mode in the Input Pin

Assignment Section).

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