ST92F124 datasheet(193/429 Pages) STMICROELECTRONICS

193 / 429 page

193/429

MULTIFUNCTION TIMER (MFT)

MULTIFUNCTION TIMER (Cont’d)

10.4.3 Input Pin Assignment

The two external inputs (TxINA and TxINB) of the

timer can be individually configured to catch a par-

ticular external event (i.e. rising edge, falling edge,

or both rising and falling edges) by programming

the two relevant bits (A0, A1 and B0, B1) for each

input in the external Input Control Register

(T_ICR).

The 16 different functional modes of the two exter-

nal inputs can be selected by programming bits

IN0 - IN3 of the T_ICR, as illustrated in Figure 39

Table 39. Input Pin Function

Some choices relating to the external input pin as-

signment are defined in conjunction with the RM0

and RM1 bits in TMR.

For input pin assignment codes which use the in-

put pins as Trigger Inputs (except for code 1010,

Trigger Up:Trigger Down), the following conditions

apply:

– a trigger signal on the TxINA input pin performs

an U/D counter load if RM0 is reset, or an exter-

nal capture if RM0 is set.

– a trigger signal on the TxINB input pin always

performs an external capture on REG1R. The

TxINB input pin is disabled when the Bivalue

Mode is set.

Note: For proper operation of the External Input

pins, the following must be observed:

– the minimum external clock/trigger pulse width

must not be less than the system clock (INTCLK)

period if the input pin is programmed as rising or

falling edge sensitive.

– the minimum external clock/trigger pulse width

must not be less than the prescaler clock period

(INTCLK/3) if the input pin is programmed as ris-

ing and falling edge sensitive (valid also in Auto

discrimination mode).

– the minimum delay between two clock/trigger

pulse active edges must be greater than the

prescaler clock period (INTCLK/3), while the

minimum delay between two consecutive clock/

trigger pulses must be greater than the system

clock (INTCLK) period.

– the minimum gate pulse width must be at least

twice the prescaler clock period (INTCLK/3).

– in Autodiscrimination mode, the minimum delay

between the input pin A pulse edge and the edge

of the input pin B pulse, must be at least equal to

the system clock (INTCLK) period.

– if a number, N, of external pulses must be count-

ed using a Compare Register in External Clock

mode, then the Compare Register must be load-

ed with the value [X +/- (N-1)], where X is the

starting counter value and the sign is chosen de-

pending on whether Up or Down count mode is

selected.

I C Reg.

IN3-IN0 bits

TxINA Input

Function

TxINB Input

Function

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

not used

Gate

not used

Trigger

Gate

Trigger

Clock Up

Up/Down

Trigger Up

Up/Down

Autodiscr.

Trigger

Ext. Clock

Trigger

not used

Trigger

not used

Trigger

Ext. Clock

not used

Ext. Clock

Trigger

Clock Down

Ext. Clock

Trigger Down

not used

Autodiscr.

Ext. Clock

Trigger

Gate

ST92F124 数据表(PDF) 193 Page - STMicroelectronics

ST92F124 数据表(HTML) 193 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ST92F124 数据表(PDF) 193 Page - STMicroelectronics

ST92F124 数据表(HTML) 193 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载