ST92F124 datasheet(203/429 Pages) STMICROELECTRONICS

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MULTIFUNCTION TIMER (MFT)

MULTIFUNCTION TIMER (Cont’d)

TIMER CONTROL REGISTER (TCR)

R248 - Read/Write

Reset value: 0000 0000 (00h)

Bit 7 = CEN: Counter enable.

This bit is ANDed with the Global Counter Enable

bit (GCEN) in the CICR register (R230). The

GCEN bit is set after the Reset cycle.

0: Stop the counter and prescaler

1: Start the counter and prescaler (without reload).

Note: Even if CEN=0, capture and loading will

take place on a trigger event.

Bit 6 = CCP0: Clear on capture.

0: No effect

1: Clear the counter and reload the prescaler on a

REG0R or REG1R capture event

Bit 5 = CCMP0: Clear on Compare.

0: No effect

1: Clear the counter and reload the prescaler on a

CMP0R compare event

Bit 4 = CCL: Counter clear.

This bit is reset by hardware after being set by

software (this bit always returns “0” when read).

0: No effect

1: Clear the counter without generating an inter-

rupt request

Bit 3 = UDC: Up/Down software selection.

If the direction of the counter is not fixed by hard-

ware (TxINA and/or TxINB pins, see par. 10.3) it

can be controlled by software using the UDC bit.

0: Down counting

1: Up counting

Bit 2 = UDCS: Up/Down count status.

This bit is read only and indicates the direction of

the counter.

0: Down counting

1: Up counting

Bit 1 = OF0: OVF/UNF state.

This bit is read only.

0: No overflow or underflow occurred

1: Overflow or underflow occurred during a Cap-

ture on Register 0

Bit 0 = CS Counter Status.

This bit is read only and indicates the status of the

counter.

0: Counter halted

1: Counter running

CEN CCP0

CCMP0 CCL UDC UDCS OF0 CS

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