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ST92F124 数据表(PDF) 204 Page - STMicroelectronics

部件名 ST92F124
功能描述  8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TM(EMULATED EEPROM), CAN 2.0B AND J1850 BLPD
PDF  429 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST92F124 数据表(HTML) 204 Page - STMicroelectronics

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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
TIMER MODE REGISTER (TMR)
R249 - Read/Write
Register Page: 10
Reset value: 0000 0000 (00h)
Bit 7 = OE1: Output 1 enable.
0: Disable the Output 1 (TxOUTB pin) and force it
high.
1: Enable the Output 1 (TxOUTB pin)
The relevant I/O bit must also be set to Alternate
Function
Bit 6 = OE0: Output 0 enable.
0: Disable the Output 0 (TxOUTA pin) and force it
high
1: Enable the Output 0 (TxOUTA pin).
The relevant I/O bit must also be set to Alternate
Function
Bit 5 = BM: Bivalue mode.
This bit works together with the RM1 and RM0 bits
to select the timer operating mode (see Table 41).
0: Disable bivalue mode
1: Enable bivalue mode
Bit 4 = RM1: REG1R mode.
This bit works together with the BM and RM0 bits
to select the timer operating mode. Refer to Table
41.
Note: This bit has no effect when the Bivalue
Mode is enabled (BM=1).
Bit 3 = RM0: REG0R mode.
This bit works together with the BM and RM1 bits
to select the timer operating mode. Refer to Table
41.
Table 41. Timer Operating Modes
Bit 2 = ECK Timer clock control.
0: The prescaler clock source is selected depend-
ing on the IN0 - IN3 bits in the T_ICR register
1: Enter Parallel mode (for Timer 1 and Timer 3
only, no effect for Timer 0 and 2). See Section
10.4.2.12.
Bit 1 = REN: Retrigger mode.
0: Enable retriggerable mode
1: Disable retriggerable mode
Bit 0 = CO: Continous/One shot mode.
0: Continuous mode (with autoreload on End of
Count condition)
1: One shot mode
70
OE1
OE0
BM
RM1
RM0
ECK
REN
C0
TMR Bits
Timer Operating Modes
BM RM1 RM0
1
x
0
Biload mode
1
x
1
Bicapture mode
00
0
Load from REG0R and Monitor on
REG1R
01
0
Load from REG0R and Capture on
REG1R
00
1
Capture on REG0R and Monitor on
REG1R
0
1
1
Capture on REG0R and REG1R
9



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