ST92F124 datasheet(208/429 Pages) STMICROELECTRONICS

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MULTIFUNCTION TIMER (MFT)

MULTIFUNCTION TIMER (Cont’d)

FLAG REGISTER (T_FLAGR)

R254 - Read/Write

Reset value: 0000 0000 (00h)

Bit 7 = CP0: Capture 0 flag.

This bit is set by hardware after a capture on

REG0R register. An interrupt is generated de-

pending on the value of the GTIEN, CP0I bits in

the IDMR register and the A0 bit in the T_FLAGR

Setting by software acts as a software load/cap-

ture to/from the REG0R register.

0: No Capture 0 event

1: Capture 0 event occurred

Bit 6 = CP1: Capture 1 flag.

This bit is set by hardware after a capture on

REG1R register. An interrupt is generated de-

pending on the value of the GTIEN, CP0I bits in

the IDMR register and the A0 bit in the T_FLAGR

Setting by software acts as a capture event on the

REG1R register, except when in Bicapture mode.

0: No Capture 1 event

1: Capture 1 event occurred

Bit 5 = CM0: Compare 0 flag.

This bit is set by hardware after a successful com-

pare on the CMP0R register. An interrupt is gener-

ated if the GTIEN and CM0I bits in the IDMR reg-

ister are set. The CM0 bit is cleared by software.

0: No Compare 0 event

1: Compare 0 event occurred

Bit 4 = CM1: Compare 1 flag.

This bit is set after a successful compare on

CMP1R register. An interrupt is generated if the

GTIEN and CM1I bits in the IDMR register are set.

The CM1 bit is cleared by software.

0: No Compare 1 event

1: Compare 1 event occurred

Bit 3 = OUF: Overflow/Underflow.

This bit is set by hardware after a counter Over/

Underflow condition. An interrupt is generated if

GTIEN and OUI=1 in the IDMR register. The OUF

bit is cleared by software.

0: No counter overflow/underflow

1: Counter overflow/underflow

Bit 2 = OCP0: Overrun on Capture 0.

This bit is set by hardware when more than one

INT/DMA requests occur before the CP0 flag is

cleared by software or whenever a capture is sim-

ulated by setting the CP0 flag by software. The

OCP0 flag is cleared by software.

0: No capture 0 overrun

1: Capture 0 overrun

Bit 1 = OCM0: Overrun on compare 0.

This bit is set by hardware when more than one

INT/DMA requests occur before the CM0 flag is

cleared by software.The OCM0 flag is cleared by

software.

0: No compare 0 overrun

1: Compare 0 overrun

Bit 0 = A0: Capture interrupt function.

This bit is set and cleared by software.

0: Configure the capture interrupt as an OR func-

tion of REG0R/REG1R captures

1: Configure the capture interrupt as an AND func-

tion of REG0R/REG1R captures

Note: When A0 is set, both CP0I and CP1I in the

IDMR register must be set to enable both capture

interrupts.

CP0

CP1

CM0

CM1

OUF

OCP0

OCM0

ST92F124 数据表(PDF) 208 Page - STMicroelectronics

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