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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)

10.5 MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)

10.5.1 Introduction

The Multiprotocol Serial Communications Inter-

face (SCI-M) offers full-duplex serial data ex-

change with a wide range of external equipment.

The SCI-M offers four operating modes: Asynchro-

nous, Asynchronous with synchronous clock, Seri-

al expansion and Synchronous.

10.5.2 Main Features

■ Full duplex synchronous and asynchronous

operation.

■ Transmit,

receive, line status, and device

address interrupt generation.

■ Integral

Baud Rate Generator capable of

dividing the input clock by any value from 2 to

216-1 (16 bit word) and generating the internal

16X data sampling clock for asynchronous

operation or the 1X clock for synchronous

operation.

■ Fully programmable serial interface:

– 5, 6, 7, or 8 bit word length.

– Even, odd, or no parity generation and detec-

tion.

– 0, 1, 1.5, 2, 2.5, 3 stop bit generation.

– Complete status reporting capabilities.

– Line break generation and detection.

■ Programmable address indication bit (wake-up

bit) and user invisible compare logic to support

multiple microcomputer networking. Optional

character search function.

■ Internal diagnostic capabilities:

– Local loopback for communications link fault

isolation.

– Auto-echo for communications link fault isola-

tion.

■ Separate interrupt/DMA channels for transmit

and receive.

■ In addition, a Synchronous mode supports:

– High speed communication

– Possibility of hardware synchronization (RTS/

DCD signals).

– Programmable polarity and stand-by level for

data SIN/SOUT.

– Programmable active edge and stand-by level

for clocks CLKOUT/RXCL.

– Programmable active levels of RTS/DCD sig-

nals.

– Full Loop-Back and Auto-Echo modes for DA-

TA, CLOCKs and CONTROLs.

Figure 106. SCI-M Block Diagram

TRANSMIT

BUFFER

SHIFT

TRANSMIT

SHIFT

RECEIVER

FUNCTION

ALTERNATE

COMPARE

ADDRESS

BUFFER

RECEIVER

DMA

CONTROLLER

CLOCK and

BAUD RATE

GENERATOR

ST9 CORE BUS

SOUT

TXCLK/CLKOUT RXCLK

SIN

VA00169A

Frame Control

and STATUS

DMA

CONTROLLER

RTS

DCD

SDS

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